Re: [PATCH RFC 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

From: Marc Zyngier <maz@kernel.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Phil Edworthy <phil.edworthy@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH RFC 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
Date: Wed, 08 Jun 2022 11:27:47 +0100	[thread overview]
Message-ID: <87leu74fh8.wl-maz@kernel.org> (raw)
In-Reply-To: <CA+V-a8sRW7oUmwOmzBx8cpk+n=cRofh3vT1cmroH_ESHN+Z3YA@mail.gmail.com>

On Tue, 07 Jun 2022 13:41:16 +0100,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Marc,
> 
> On Mon, Jun 6, 2022 at 4:41 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Fri, 27 May 2022 12:05:38 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > >
> > > I sometimes still see an interrupt miss!
> > >
> > > As per [0], we first need to claim the interrupt by reading the claim
> > > register which needs to be done in the ack callback (which should be
> > > doable) for edge interrupts, but the problem arises in the chained
> > > handler callback where it does claim the interrupt by reading the
> > > claim register.
> > >
> > > static void plic_handle_irq(struct irq_desc *desc)
> > > {
> > >     struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > >     struct irq_chip *chip = irq_desc_get_chip(desc);
> > >     void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
> > >     irq_hw_number_t hwirq;
> > >
> > >     WARN_ON_ONCE(!handler->present);
> > >
> > >     chained_irq_enter(chip, desc);
> > >
> > >     while ((hwirq = readl(claim))) {
> > >         int err = generic_handle_domain_irq(handler->priv->irqdomain,
> > >                             hwirq);
> > >         if (unlikely(err))
> > >             pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
> > >                     hwirq);
> > >     }
> > >
> > >     chained_irq_exit(chip, desc);
> > > }
> > >
> > > I was thinking I would get around by getting the irqdata in
> > > plic_handle_irq() callback using the irq_desc (struct irq_data *d =
> > > &desc->irq_data;) and check the d->hwirq but this will be always 9.
> > >
> > >         plic: interrupt-controller@12c00000 {
> > >             compatible = "renesas-r9a07g043-plic";
> > >             #interrupt-cells = <2>;
> > >             #address-cells = <0>;
> > >             riscv,ndev = <543>;
> > >             interrupt-controller;
> > >             reg = <0x0 0x12c00000 0 0x400000>;
> > >             clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > >             clock-names = "plic100ss";
> > >             power-domains = <&cpg>;
> > >             resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > >             interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> > >         };
> > >
> > > Any pointers on how this could be done sanely.
> >
> > Why doesn't the chained interrupt also get the ack-aware irq_chip?
> >
> Sorry for being naive, could you please elaborate on this.

There are two main reasons why the above code fails: these interrupts
are not using either

- the irqchip you think they are using (which one then?),

- the interrupt flow they should be using.

Dumping /sys/kernel/debug/irq/irqs/$IRQ should give you a clue.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.