From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAC52C2D0DE for ; Thu, 2 Jan 2020 00:10:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F3F22072C for ; Thu, 2 Jan 2020 00:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727441AbgABAKc (ORCPT ); Wed, 1 Jan 2020 19:10:32 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:40515 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727393AbgABAKc (ORCPT ); Wed, 1 Jan 2020 19:10:32 -0500 Received: from [10.18.38.198] (10.18.38.198) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Thu, 2 Jan 2020 08:10:52 +0800 Subject: Re: [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver To: Martin Blumenstingl CC: Rob Herring , Victor Wan , Jianxin Pan , Neil Armstrong , Stephen Boyd , Kevin Hilman , Michael Turquette , , Yue Wang , Qiufang Dai , , Liang Yang , Jian Hu , Xingyu Chen , Greg Kroah-Hartman , Carlo Caione , , , Jerome Brunet References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> <1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com> From: Hanjie Lin Message-ID: <8defdb9d-7032-7360-0904-a63d52d16ba6@amlogic.com> Date: Thu, 2 Jan 2020 08:10:51 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.38.198] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2019/12/28 0:40, Martin Blumenstingl wrote: > Hi Hanjie, > > overall this looks good to me and I have one question > > On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin wrote: > [...] >> + if (priv->soc_id == MESON_SOC_A1) >> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; > ...here we have some CLK_SEL bit > > [...] >> - priv->clk = devm_clk_get(dev, "xtal"); >> - if (IS_ERR(priv->clk)) >> - return PTR_ERR(priv->clk); >> + if (priv->soc_id == MESON_SOC_G12A) { >> + priv->clk = devm_clk_get(dev, "xtal"); >> + if (IS_ERR(priv->clk)) >> + return PTR_ERR(priv->clk); >> + } > but here we don't need any parent/input clock? > does this mean that the USB2 PHY on the A1 SoC doesn't have any clock > inputs? how does it generate the correct clock for itself then? > Hi Martin Actually, there is a "xtal_usb_phy" clock in A1 ctrl driver, it seems it's better to be in the A1 phy driver. I will move that clock here in next version. Thanks, Hanjie > > Martin > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic > > . >