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Thu, 1 Apr 2021 08:51:14 +0000 From: Damien Le Moal To: Greentime Hu , "paul.walmsley@sifive.com" , "hes@sifive.com" , "erik.danie@sifive.com" , "zong.li@sifive.com" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "aou@eecs.berkeley.edu" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "lorenzo.pieralisi@arm.com" , "p.zabel@pengutronix.de" , "alex.dewar90@gmail.com" , "khilman@baylibre.com" , "hayashi.kunihiko@socionext.com" , "vidyas@nvidia.com" , "jh80.chung@samsung.com" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "helgaas@kernel.org" Subject: Re: [PATCH v4 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver Thread-Topic: [PATCH v4 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver Thread-Index: AQHXJryVLlFTcA0IMUCQSslO/VnpAQ== Date: Thu, 1 Apr 2021 08:51:14 +0000 Message-ID: References: <20210401060054.40788-1-greentime.hu@sifive.com> <20210401060054.40788-6-greentime.hu@sifive.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: sifive.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL0PR04MB6514.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bca90344-e5e1-49b9-0ee9-08d8f4eb4ea0 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Apr 2021 08:51:14.5723 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wokpHxf31FKtdaKDH/XAqmm31ipdrh6XByRCGER+Y52myqkEshLTXDJDJpbzNn6Y42ANmRQfFvGaC5qQjRQVxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6894 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2021/04/01 15:02, Greentime Hu wrote:=0A= > From: Paul Walmsley =0A= > =0A= > Add driver for the SiFive FU740 PCIe host controller.=0A= > This controller is based on the DesignWare PCIe core.=0A= > =0A= > Signed-off-by: Paul Walmsley =0A= > Co-developed-by: Henry Styles =0A= > Signed-off-by: Henry Styles =0A= > Co-developed-by: Erik Danie =0A= > Signed-off-by: Erik Danie =0A= > Co-developed-by: Greentime Hu =0A= > Signed-off-by: Greentime Hu =0A= > ---=0A= > drivers/pci/controller/dwc/Kconfig | 9 +=0A= > drivers/pci/controller/dwc/Makefile | 1 +=0A= > drivers/pci/controller/dwc/pcie-fu740.c | 324 ++++++++++++++++++++++++= =0A= > 3 files changed, 334 insertions(+)=0A= > create mode 100644 drivers/pci/controller/dwc/pcie-fu740.c=0A= > =0A= > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/= dwc/Kconfig=0A= > index 22c5529e9a65..0a37d21ed64e 100644=0A= > --- a/drivers/pci/controller/dwc/Kconfig=0A= > +++ b/drivers/pci/controller/dwc/Kconfig=0A= > @@ -318,4 +318,13 @@ config PCIE_AL=0A= > required only for DT-based platforms. ACPI platforms with the=0A= > Annapurna Labs PCIe controller don't need to enable this.=0A= > =0A= > +config PCIE_FU740=0A= > + bool "SiFive FU740 PCIe host controller"=0A= > + depends on PCI_MSI_IRQ_DOMAIN=0A= > + depends on SOC_SIFIVE || COMPILE_TEST=0A= > + select PCIE_DW_HOST=0A= > + help=0A= > + Say Y here if you want PCIe controller support for the SiFive=0A= > + FU740.=0A= > +=0A= > endmenu=0A= > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller= /dwc/Makefile=0A= > index a751553fa0db..625f6aaeb5b8 100644=0A= > --- a/drivers/pci/controller/dwc/Makefile=0A= > +++ b/drivers/pci/controller/dwc/Makefile=0A= > @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o=0A= > obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o=0A= > obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o=0A= > obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o=0A= > +obj-$(CONFIG_PCIE_FU740) +=3D pcie-fu740.o=0A= > obj-$(CONFIG_PCI_IMX6) +=3D pci-imx6.o=0A= > obj-$(CONFIG_PCIE_SPEAR13XX) +=3D pcie-spear13xx.o=0A= > obj-$(CONFIG_PCI_KEYSTONE) +=3D pci-keystone.o=0A= > diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/contro= ller/dwc/pcie-fu740.c=0A= > new file mode 100644=0A= > index 000000000000..ebbcbda97490=0A= > --- /dev/null=0A= > +++ b/drivers/pci/controller/dwc/pcie-fu740.c=0A= > @@ -0,0 +1,324 @@=0A= > +// SPDX-License-Identifier: GPL-2.0=0A= > +/*=0A= > + * FU740 DesignWare PCIe Controller integration=0A= > + * Copyright (C) 2019-2021 SiFive, Inc.=0A= > + * Paul Walmsley=0A= > + * Greentime Hu=0A= > + *=0A= > + * Based in part on the i.MX6 PCIe host controller shim which is:=0A= > + *=0A= > + * Copyright (C) 2013 Kosagi=0A= > + * https://www.kosagi.com=0A= > + */=0A= > +=0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +#include =0A= > +=0A= > +#include "pcie-designware.h"=0A= > +=0A= > +#define to_fu740_pcie(x) dev_get_drvdata((x)->dev)=0A= > +=0A= > +struct fu740_pcie {=0A= > + struct dw_pcie pci;=0A= > + void __iomem *mgmt_base;=0A= > + struct gpio_desc *reset;=0A= > + struct gpio_desc *pwren;=0A= > + struct clk *pcie_aux;=0A= > + struct reset_control *rst;=0A= > +};=0A= > +=0A= > +#define SIFIVE_DEVICESRESETREG 0x28=0A= > +=0A= > +#define PCIEX8MGMT_PERST_N 0x0=0A= > +#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10=0A= > +#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18=0A= > +#define PCIEX8MGMT_DEVICE_TYPE 0x708=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890=0A= > +#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0=0A= > +#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8=0A= > +=0A= > +#define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)=0A= > +#define PCIEX8MGMT_PHY_LOS_THRSHLD BIT(5)=0A= > +#define PCIEX8MGMT_PHY_TERM_EN BIT(9)=0A= > +#define PCIEX8MGMT_PHY_TERM_ACDC BIT(10)=0A= > +#define PCIEX8MGMT_PHY_EN BIT(11)=0A= > +#define PCIEX8MGMT_PHY_INIT_VAL (PCIEX8MGMT_PHY_CDR_TRACK_EN|\=0A= > + PCIEX8MGMT_PHY_LOS_THRSHLD|\=0A= > + PCIEX8MGMT_PHY_TERM_EN|\=0A= > + PCIEX8MGMT_PHY_TERM_ACDC|\=0A= > + PCIEX8MGMT_PHY_EN)=0A= > +=0A= > +#define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008=0A= > +#define PCIEX8MGMT_PHY_LANE_OFF 0x100=0A= > +#define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD= _IN_3 + 0x100 * 0)=0A= > +#define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD= _IN_3 + 0x100 * 1)=0A= > +#define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD= _IN_3 + 0x100 * 2)=0A= > +#define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD= _IN_3 + 0x100 * 3)=0A= > +=0A= > +static void fu740_pcie_assert_reset(struct fu740_pcie *afp)=0A= > +{=0A= > + /* Assert PERST_N GPIO */=0A= > + gpiod_set_value_cansleep(afp->reset, 0);=0A= > + /* Assert controller PERST_N */=0A= > + writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);=0A= > +}=0A= > +=0A= > +static void fu740_pcie_deassert_reset(struct fu740_pcie *afp)=0A= > +{=0A= > + /* Deassert controller PERST_N */=0A= > + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);=0A= > + /* Deassert PERST_N GPIO */=0A= > + gpiod_set_value_cansleep(afp->reset, 1);=0A= > +}=0A= > +=0A= > +static void fu740_pcie_power_on(struct fu740_pcie *afp)=0A= > +{=0A= > + gpiod_set_value_cansleep(afp->pwren, 1);=0A= > + /*=0A= > + * Ensure that PERST has been asserted for at least 100 ms.=0A= > + * Section 2.2 of PCI Express Card Electromechanical Specification=0A= > + * Revision 3.0=0A= > + */=0A= > + msleep(100);=0A= > +}=0A= > +=0A= > +static void fu740_pcie_drive_reset(struct fu740_pcie *afp)=0A= > +{=0A= > + fu740_pcie_assert_reset(afp);=0A= > + fu740_pcie_power_on(afp);=0A= > + fu740_pcie_deassert_reset(afp);=0A= > +}=0A= > +=0A= > +static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr,=0A= > + const uint16_t wrdata, struct fu740_pcie *afp)=0A= > +{=0A= > + struct device *dev =3D afp->pci.dev;=0A= > + void __iomem *phy_cr_para_addr;=0A= > + void __iomem *phy_cr_para_wr_data;=0A= > + void __iomem *phy_cr_para_wr_en;=0A= > + void __iomem *phy_cr_para_ack;=0A= > + int ret, val;=0A= > +=0A= > + /* Setup */=0A= > + if (phy) {=0A= > + phy_cr_para_addr =3D afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;=0A= > + phy_cr_para_wr_data =3D afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DA= TA;=0A= > + phy_cr_para_wr_en =3D afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;= =0A= > + phy_cr_para_ack =3D afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;=0A= > + } else {=0A= > + phy_cr_para_addr =3D afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;=0A= > + phy_cr_para_wr_data =3D afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DA= TA;=0A= > + phy_cr_para_wr_en =3D afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;= =0A= > + phy_cr_para_ack =3D afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;=0A= > + }=0A= > +=0A= > + writel_relaxed(addr, phy_cr_para_addr);=0A= > + writel_relaxed(wrdata, phy_cr_para_wr_data);=0A= > + writel_relaxed(1, phy_cr_para_wr_en);=0A= > +=0A= > + /* Wait for wait_idle */=0A= > + ret =3D readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000);=0A= > + if (ret)=0A= > + dev_err(dev, "Wait for wait_ilde state failed!\n");=0A= =0A= This is a void function. What is the point of these dev_err() if you do not= =0A= return an error or process the failure in any way ? Change this to dev_warn= ()=0A= may be ?=0A= =0A= > +=0A= > + /* Clear */=0A= > + writel_relaxed(0, phy_cr_para_wr_en);=0A= > +=0A= > + /* Wait for ~wait_idle */=0A= > + ret =3D readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000);=0A= > + if (ret)=0A= > + dev_err(dev, "Wait for !wait_ilde state failed!\n");=0A= =0A= Same as above.=0A= =0A= > +}=0A= > +=0A= > +static void fu740_pcie_init_phy(struct fu740_pcie *afp)=0A= > +{=0A= > + /* Enable phy cr_para_sel interfaces */=0A= > + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);=0A= > + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);=0A= > +=0A= > + /*=0A= > + * Wait 10 cr_para cycles to guarantee that the registers are ready=0A= > + * to be edited.=0A= > + */=0A= > + ndelay(10);=0A= > +=0A= > + /* Set PHY AC termination mode */=0A= > + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL= , afp);=0A= > +}=0A= > +=0A= > +static void fu740_pcie_ltssm_enable(struct device *dev)=0A= > +{=0A= > + struct fu740_pcie *afp =3D dev_get_drvdata(dev);=0A= > +=0A= > + /* Enable LTSSM */=0A= > + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);=0A= > +}=0A= > +=0A= > +static int fu740_pcie_start_link(struct dw_pcie *pci)=0A= > +{=0A= > + struct device *dev =3D pci->dev;=0A= =0A= No need for this variable.=0A= =0A= > +=0A= > + /* Start LTSSM. */=0A= > + fu740_pcie_ltssm_enable(dev);=0A= > + return 0;=0A= > +}=0A= > +=0A= > +static int fu740_pcie_host_init(struct pcie_port *pp)=0A= > +{=0A= > + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp);=0A= > + struct fu740_pcie *afp =3D to_fu740_pcie(pci);=0A= > + struct device *dev =3D pci->dev;=0A= > + int ret;=0A= > +=0A= > + /* Power on reset */=0A= > + fu740_pcie_drive_reset(afp);=0A= > +=0A= > + /* Enable pcieauxclk */=0A= > + ret =3D clk_prepare_enable(afp->pcie_aux);=0A= > + if (ret)=0A= > + dev_err(dev, "unable to enable pcie_aux clock\n");=0A= =0A= No bailing out ? Without a clock, is this going to work ?=0A= If that is not a problem, then I would suggest a dev_warn() here.=0A= =0A= > +=0A= > + /*=0A= > + * Assert hold_phy_rst (hold the controller LTSSM in reset after=0A= > + * power_up_rst_n for register programming with cr_para)=0A= > + */=0A= > + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);=0A= > +=0A= > + /* Deassert power_up_rst_n */=0A= > + ret =3D reset_control_deassert(afp->rst);=0A= > + if (ret)=0A= > + dev_err(dev, "unable to deassert pcie_power_up_rst_n\n");=0A= =0A= Same as above.=0A= =0A= > +=0A= > + fu740_pcie_init_phy(afp);=0A= > +=0A= > + /* Disable pcieauxclk */=0A= > + clk_disable_unprepare(afp->pcie_aux);=0A= > + /* Clear hold_phy_rst */=0A= > + writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);=0A= > + /* Enable pcieauxclk */=0A= > + ret =3D clk_prepare_enable(afp->pcie_aux);=0A= > + /* Set RC mode */=0A= > + writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);=0A= > +=0A= > + return 0;=0A= > +}=0A= > +=0A= > +static const struct dw_pcie_host_ops fu740_pcie_host_ops =3D {=0A= > + .host_init =3D fu740_pcie_host_init,=0A= > +};=0A= > +=0A= > +static const struct dw_pcie_ops dw_pcie_ops =3D {=0A= > + .start_link =3D fu740_pcie_start_link,=0A= > +};=0A= > +=0A= > +static int fu740_pcie_probe(struct platform_device *pdev)=0A= > +{=0A= > + struct device *dev =3D &pdev->dev;=0A= > + struct dw_pcie *pci;=0A= > + struct fu740_pcie *afp;=0A= > + int ret;=0A= > +=0A= > + afp =3D devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL);=0A= > + if (!afp)=0A= > + return -ENOMEM;=0A= > + pci =3D &afp->pci;=0A= > + pci->dev =3D dev;=0A= > + pci->ops =3D &dw_pcie_ops;=0A= > + pci->pp.ops =3D &fu740_pcie_host_ops;=0A= > +=0A= > + /* SiFive specific region: mgmt */=0A= > + afp->mgmt_base =3D devm_platform_ioremap_resource_byname(pdev, "mgmt");= =0A= > + if (IS_ERR(afp->mgmt_base))=0A= > + return PTR_ERR(afp->mgmt_base);=0A= > +=0A= > + /* Fetch GPIOs */=0A= > + afp->reset =3D devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LO= W);=0A= > + if (IS_ERR(afp->reset)) {=0A= > + dev_err(dev, "unable to get reset-gpios\n");=0A= > + return ret;=0A= > + }=0A= > + afp->pwren =3D devm_gpiod_get_optional(dev, "pwren-gpios", GPIOD_OUT_LO= W);=0A= > + if (IS_ERR(afp->pwren)) {=0A= > + dev_err(dev, "unable to get pwren-gpios\n");=0A= > + return ret;=0A= =0A= Why not return dev_err_probe(...); ? Same for the returns above.=0A= =0A= > + }=0A= > +=0A= > + /* Fetch clocks */=0A= > + afp->pcie_aux =3D devm_clk_get(dev, "pcie_aux");=0A= > + if (IS_ERR(afp->pcie_aux))=0A= > + return dev_err_probe(dev, PTR_ERR(afp->pcie_aux),=0A= > + "pcie_aux clock source missing or invalid\n");=0A= > +=0A= > + /* Fetch reset */=0A= > + afp->rst =3D devm_reset_control_get_exclusive(dev, NULL);=0A= > + if (IS_ERR(afp->rst))=0A= > + return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n");= =0A= > +=0A= > + platform_set_drvdata(pdev, afp);=0A= > +=0A= > + ret =3D dw_pcie_host_init(&pci->pp);=0A= > + if (ret < 0)=0A= > + return ret;=0A= =0A= You can simplify this with a simple:=0A= =0A= return dw_pcie_host_init(&pci->pp);=0A= =0A= > +=0A= > + return 0;=0A= > +}=0A= > +=0A= > +static void fu740_pcie_shutdown(struct platform_device *pdev)=0A= > +{=0A= > + struct fu740_pcie *afp =3D platform_get_drvdata(pdev);=0A= > +=0A= > + /* Bring down link, so bootloader gets clean state in case of reboot */= =0A= > + fu740_pcie_assert_reset(afp);=0A= > +}=0A= > +=0A= > +static const struct of_device_id fu740_pcie_of_match[] =3D {=0A= > + { .compatible =3D "sifive,fu740-pcie", },=0A= > + {},=0A= > +};=0A= > +=0A= > +static struct platform_driver fu740_pcie_driver =3D {=0A= > + .driver =3D {=0A= > + .name =3D "fu740-pcie",=0A= > + .of_match_table =3D fu740_pcie_of_match,=0A= > + .suppress_bind_attrs =3D true,=0A= > + },=0A= > + .probe =3D fu740_pcie_probe,=0A= > + .shutdown =3D fu740_pcie_shutdown,=0A= > +};=0A= > +=0A= > +builtin_platform_driver(fu740_pcie_driver);=0A= > =0A= =0A= =0A= -- =0A= Damien Le Moal=0A= Western Digital Research=0A=