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Fri, 27 Aug 2021 07:55:05 +0000 From: "Demakkanavar, Kenchappa" To: Rob Herring CC: "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "dinguyen@kernel.org" , "Zhou, Furong" , "kris.pan@linux.intel.com" , "Pan, Kris" , "mgross@linux.intel.com" , "Gross, Mark" Subject: RE: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC Thread-Topic: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC Thread-Index: AQHXfSdUc5B0XBEUTEe+3UCDr3sM3qtabHqAgCy/a0A= Date: Fri, 27 Aug 2021 07:55:05 +0000 Message-ID: References: <1626758569-27176-1-git-send-email-kenchappa.demakkanavar@intel.com> <1626758569-27176-4-git-send-email-kenchappa.demakkanavar@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB2661.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc32a15f-1a96-4126-6407-08d9692ffbc0 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Aug 2021 07:55:05.6305 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tphYf7CAwnYfjrEAPoElYySH+gE3oKH2IXrZs0+VYxPdN7QixqohIZkSD+3ytQB0BiqghLksty5KPrE6lwIWeFwkDNRRD1L8rJWO4cxmOXzQsQoCDI7d40GtiqiS5dsT X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4276 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Rob, Thanks for your time in providing feedback.=20 Please find my reply in-lined below. Thanks & Regards, Kenchappa S. D. > -----Original Message----- > From: Rob Herring > Sent: Friday, July 30, 2021 1:23 AM > To: Demakkanavar, Kenchappa > Cc: will@kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org; > Zhou, Furong ; kris.pan@linux.intel.com; Pan, Kris > ; mgross@linux.intel.com; Gross, Mark > > Subject: Re: [PATCH V2 3/3] arm64: dts: add initial device tree for Thund= er Bay > SoC >=20 > On Tue, Jul 20, 2021 at 10:52:49AM +0530, > kenchappa.demakkanavar@intel.com wrote: > > From: "Demakkanavar, Kenchappa" > > > > Add initial device tree for Intel Movidius SoC code-named Thunder Bay. > > > > This initial DT includes nodes for 4 CPU clusters with 4 Cortex-A53 > > cores per cluster, UARTs, GIC, ARM Timer and PSCI. >=20 > Make sure you run 'make dtbs_check' on these. Sure. Will post clean patches in next version. >=20 > There shouldn't be any dtc warnings and or undocumented compatible warnin= gs > at a minimum. Sure. Will post clean patches in next version. >=20 > > thunderbay-soc.dtsi - Thunder Bay SoC dtsi file > > hddl_hybrid_4s.dts - Thunder Bay full configuration board dts > > with 4 VPU processors > > hddl_hybrid_2s_02.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 0 and slice 2 enabled) > > hddl_hybrid_2s_03.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 0 and slice 3 enabled) > > hddl_hybrid_2s_12.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 1 and slice 2 enabled) > > hddl_hybrid_2s_13.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 1 and slice 3 enabled) > > > > Signed-off-by: Demakkanavar, Kenchappa > > > > --- > > MAINTAINERS | 2 + > > arch/arm64/boot/dts/intel/Makefile | 6 + > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts | 54 ++++++ > > arch/arm64/boot/dts/intel/thunderbay-soc.dtsi | 243 > ++++++++++++++++++++++++ > > 8 files changed, 477 insertions(+) > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > > > diff --git a/MAINTAINERS b/MAINTAINERS index 041f9a0..68317f0 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1996,6 +1996,8 @@ ARM/INTEL THUNDERBAY ARCHITECTURE > > M: Demakkanavar, Kenchappa > > S: Maintained > > F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > > +F: arch/arm64/boot/dts/intel/hddl* > > +F: arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > > > ARM/INTEL XSC3 (MANZANO) ARM CORE > > M: Lennert Buytenhek > > diff --git a/arch/arm64/boot/dts/intel/Makefile > > b/arch/arm64/boot/dts/intel/Makefile > > index 0b54774..767b74b 100644 > > --- a/arch/arm64/boot/dts/intel/Makefile > > +++ b/arch/arm64/boot/dts/intel/Makefile > > @@ -3,3 +3,9 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D > socfpga_agilex_socdk.dtb \ > > socfpga_agilex_socdk_nand.dtb \ > > socfpga_n5x_socdk.dtb > > dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb > > + > > +dtb-$(CONFIG_ARCH_THUNDERBAY) +=3D hddl_hybrid_4s.dtb \ > > + hddl_hybrid_2s_02.dtb \ > > + hddl_hybrid_2s_03.dtb \ > > + hddl_hybrid_2s_12.dtb \ > > + hddl_hybrid_2s_13.dtb > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > new file mode 100644 > > index 0000000..f907ddd > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board. > > + * > > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 2 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model =3D "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible =3D "intel,thunderbay"; > > + > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + aliases { > > + serial0 =3D &uart0; > > + serial1 =3D &uart1; >=20 > Why do you have an alias to a disabled node? Ok. Will remove this.=20 >=20 > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { >=20 > Lowercase hex on unit-addresses. Ok. >=20 > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > new file mode 100644 > > index 0000000..01a3d4c > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 3 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model =3D "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible =3D "intel,thunderbay"; >=20 > This should have a board specific compatible. Not sure if you need 1 or > 4 though. If the VPU slice stuff is determined elsewhere then 1 is enough= . Since minimum dts will boot for both 4 slice VPU SoC and 2 slice VPU SoC, I= will start with single compatible string now.=20 Also minimum dts for 2 VPU slices are same, I will submit common single dts= for 2 VPU slice boards in next version. >=20 > > + > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + aliases { > > + serial0 =3D &uart0; > > + serial1 =3D &uart1; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > new file mode 100644 > > index 0000000..e31db16 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 2 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model =3D "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible =3D "intel,thunderbay"; > > + > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + aliases { > > + serial0 =3D &uart0; > > + serial1 =3D &uart1; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > new file mode 100644 > > index 0000000..6529664 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 3 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model =3D "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible =3D "intel,thunderbay"; > > + > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + aliases { > > + serial0 =3D &uart0; > > + serial1 =3D &uart1; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; >=20 > These all look the same, why do we need 4 copies? Full dts will have VPU slice specific dts nodes. Since minimum dts for 2 VP= U slices are same, I will submit common single dts for 2 VPU slice boards i= n next version. >=20 > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > new file mode 100644 > > index 0000000..561ecea > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > @@ -0,0 +1,54 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Full > > +configuration > > + * board > > + * > > + * DDR 8GB + 8GB + 4GB + 4GB with four vpu slices */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model =3D "Intel Thunder Bay Hybrid HDDL Full Board"; > > + compatible =3D "intel,thunderbay"; > > + > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + aliases { > > + serial0 =3D &uart0; > > + serial1 =3D &uart1; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type =3D "memory"; > > + /* 8GB of DDR memory */ > > + reg =3D <0x12 0x0 0x2 0x0>; > > + }; > > + > > + memory@1400000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x14 0x0 0x1 0x0>; > > + }; > > + > > + memory@1500000000 { > > + device_type =3D "memory"; > > + /* 4GB of DDR memory */ > > + reg =3D <0x15 0x0 0x1 0x0>; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > new file mode 100644 > > index 0000000..834200d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > @@ -0,0 +1,243 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Thunder Bay SoC */ > > + > > +#include > > + > > +/ { > > + > > + compatible =3D "intel,thunderbay"; > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + interrupt-parent =3D <&gic>; > > + > > + cpus { > > + #address-cells =3D <2>; > > + #size-cells =3D <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu =3D <&CPU0>; > > + }; > > + core1 { > > + cpu =3D <&CPU1>; > > + }; > > + core2 { > > + cpu =3D <&CPU2>; > > + }; > > + core3 { > > + cpu =3D <&CPU3>; > > + }; > > + }; > > + cluster1 { > > + core0 { > > + cpu =3D <&CPU4>; > > + }; > > + core1 { > > + cpu =3D <&CPU5>; > > + }; > > + core2 { > > + cpu =3D <&CPU6>; > > + }; > > + core3 { > > + cpu =3D <&CPU7>; > > + }; > > + }; > > + cluster2 { > > + core0 { > > + cpu =3D <&CPU8>; > > + }; > > + core1 { > > + cpu =3D <&CPU9>; > > + }; > > + core2 { > > + cpu =3D <&CPU10>; > > + }; > > + core3 { > > + cpu =3D <&CPU11>; > > + }; > > + }; > > + cluster3 { > > + core0 { > > + cpu =3D <&CPU12>; > > + }; > > + core1 { > > + cpu =3D <&CPU13>; > > + }; > > + core2 { > > + cpu =3D <&CPU14>; > > + }; > > + core3 { > > + cpu =3D <&CPU15>; > > + }; > > + }; > > + }; > > + > > + CPU0: cpu@0 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x0>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU1: cpu@1 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x1>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU2: cpu@2 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x2>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU3: cpu@3 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x3>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU4: cpu@100 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x100>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU5: cpu@101 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x101>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU6: cpu@102 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x102>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU7: cpu@103 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x103>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU8: cpu@200 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x200>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU9: cpu@201 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x201>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU10: cpu@202 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x202>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU11: cpu@203 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x203>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU12: cpu@300 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x300>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU13: cpu@301 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x301>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU14: cpu@302 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x302>; > > + enable-method =3D "psci"; > > + }; > > + > > + CPU15: cpu@303 { > > + compatible =3D "arm,cortex-a53"; > > + device_type =3D "cpu"; > > + reg =3D <0x0 0x303>; > > + enable-method =3D "psci"; > > + }; > > + }; > > + > > + psci { > > + compatible =3D "arm,psci-0.2"; >=20 > PSCI 1.0 has been out for 6 years... I will update this after verifying our ATF supported PSCI version =20 >=20 > > + method =3D "smc"; > > + }; > > + > > + gic: interrupt-controller@88400000 { > > + compatible =3D "arm,gic-v3"; > > + interrupt-controller; > > + #interrupt-cells =3D <3>; > > + reg =3D <0x0 0x88400000 0x0 0x200000>, /* GICD */ > > + <0x0 0x88600000 0x0 0x200000>; /* GICR */ > > + /* VGIC maintenance interrupt */ > > + interrupts =3D ; > > + }; > > + > > + timer { > > + compatible =3D "arm,armv8-timer"; > > + /* Secure, non-secure, virtual, and hypervisor */ > > + interrupts =3D , > > + , > > + , > > + ; > > + }; > > + > > + soc { > > + compatible =3D "simple-bus"; > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + ranges; > > + dma-ranges; > > + > > + uart0: serial@80460000 { > > + compatible =3D "snps,dw-apb-uart"; > > + reg =3D <0x0 0x80460000 0x0 0x100>; > > + interrupts =3D ; > > + clock-frequency =3D <50000000>; > > + reg-shift =3D <2>; > > + reg-io-width =3D <4>; > > + }; > > + > > + uart1: serial@80470000 { > > + compatible =3D "snps,dw-apb-uart"; > > + reg =3D <0x0 0x80470000 0x0 0x100>; > > + interrupts =3D ; > > + clock-frequency =3D <50000000>; > > + reg-shift =3D <2>; > > + reg-io-width =3D <4>; > > + status =3D "disabled"; > > + }; > > + }; > > +}; > > -- > > 2.7.4 > > > >