devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node
@ 2020-09-30  5:11 Billy Tsai
  2020-09-30  9:06 ` [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region Billy Tsai
  2020-10-01  0:36 ` [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Andrew Jeffery
  0 siblings, 2 replies; 7+ messages in thread
From: Billy Tsai @ 2020-09-30  5:11 UTC (permalink / raw)
  To: robh+dt, joel, andrew, devicetree, linux-arm-kernel,
	linux-aspeed, linux-kernel
  Cc: BMC-SW

This commit add two sgpiom and two sgpios node into aspeed-g6.dtsi
and change the register range of gpio0 to fix the hardware design.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 51 +++++++++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..00237daec2a1 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -357,7 +357,7 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				compatible = "aspeed,ast2600-gpio";
-				reg = <0x1e780000 0x800>;
+				reg = <0x1e780000 0x500>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				gpio-ranges = <&pinctrl 0 0 208>;
 				ngpios = <208>;
@@ -365,6 +365,55 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
+			sgpiom0: sgpiom@1e780500 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom";
+				reg = <0x1e780500 0x100>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <128>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm1_default>;
+				status = "disabled";
+			};
+
+			sgpiom1: sgpiom@1e780600 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpiom";
+				reg = <0x1e780600 0x100>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				ngpios = <80>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+				interrupt-controller;
+				bus-frequency = <12000000>;
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sgpm2_default>;
+				status = "disabled";
+			};
+
+			sgpios0: sgpios@1e780700 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpios";
+				reg = <0x1e780700 0x40>;
+				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+			};
+
+			sgpios1: sgpios@1e780740 {
+				#gpio-cells = <2>;
+				gpio-controller;
+				compatible = "aspeed,ast2600-sgpios";
+				reg = <0x1e780740 0x40>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&syscon ASPEED_CLK_APB2>;
+			};
 
 			gpio1: gpio@1e780800 {
 				#gpio-cells = <2>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region
  2020-09-30  5:11 [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Billy Tsai
@ 2020-09-30  9:06 ` Billy Tsai
  2020-10-01  0:12   ` Andrew Jeffery
  2020-10-01  0:36 ` [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Andrew Jeffery
  1 sibling, 1 reply; 7+ messages in thread
From: Billy Tsai @ 2020-09-30  9:06 UTC (permalink / raw)
  To: robh+dt, joel, andrew, devicetree, linux-arm-kernel,
	linux-aspeed, linux-kernel
  Cc: BMC-SW

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..b9ec8b579f73 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -357,7 +357,7 @@
 				#gpio-cells = <2>;
 				gpio-controller;
 				compatible = "aspeed,ast2600-gpio";
-				reg = <0x1e780000 0x800>;
+				reg = <0x1e780000 0x500>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				gpio-ranges = <&pinctrl 0 0 208>;
 				ngpios = <208>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region
  2020-09-30  9:06 ` [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region Billy Tsai
@ 2020-10-01  0:12   ` Andrew Jeffery
  2020-10-01  0:32     ` Andrew Jeffery
  0 siblings, 1 reply; 7+ messages in thread
From: Andrew Jeffery @ 2020-10-01  0:12 UTC (permalink / raw)
  To: Billy Tsai, Rob Herring, Joel Stanley, devicetree,
	linux-arm-kernel, linux-aspeed, linux-kernel
  Cc: BMC-SW

Hi Billy,

On Wed, 30 Sep 2020, at 18:36, Billy Tsai wrote:
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 97ca743363d7..b9ec8b579f73 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -357,7 +357,7 @@
>  				#gpio-cells = <2>;
>  				gpio-controller;
>  				compatible = "aspeed,ast2600-gpio";
> -				reg = <0x1e780000 0x800>;
> +				reg = <0x1e780000 0x500>;

We took the 0x800 value from the memory space layout table in the datasheet for 
the 2600. Should that be updated too? Or are you just limiting the region to 
the registers currently described rather than the allocated address space?

Cheers,

Andrew

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region
  2020-10-01  0:12   ` Andrew Jeffery
@ 2020-10-01  0:32     ` Andrew Jeffery
  2020-10-01  1:11       ` Ryan Chen
  0 siblings, 1 reply; 7+ messages in thread
From: Andrew Jeffery @ 2020-10-01  0:32 UTC (permalink / raw)
  To: Billy Tsai, Rob Herring, Joel Stanley, devicetree,
	linux-arm-kernel, linux-aspeed, linux-kernel, Ryan Chen
  Cc: BMC-SW



On Thu, 1 Oct 2020, at 09:42, Andrew Jeffery wrote:
> Hi Billy,
> 
> On Wed, 30 Sep 2020, at 18:36, Billy Tsai wrote:
> > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > ---
> >  arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index 97ca743363d7..b9ec8b579f73 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -357,7 +357,7 @@
> >  				#gpio-cells = <2>;
> >  				gpio-controller;
> >  				compatible = "aspeed,ast2600-gpio";
> > -				reg = <0x1e780000 0x800>;
> > +				reg = <0x1e780000 0x500>;
> 
> We took the 0x800 value from the memory space layout table in the datasheet for 
> the 2600. Should that be updated too? Or are you just limiting the region to 
> the registers currently described rather than the allocated address space?

Ah, actually, I see what's going on. We really have this layout (taking some liberties):

0x1e785000 - 0x1e785500: PGPIO 3.3V
0x1e785500 - 0x1e785600: SGPM1
0x1e785600 - 0x1e785700: SGPM2
0x1e785700 - 0x1e785740: SPGS1
0x1e785740 - 0x1e785780: SPGS2
0x1e785800 - 0x1e786000: PGPIO 1.8V

Ryan: Can you change the address space layout table to reflect this? That way it
still functions as a quick - but accurate - reference.

Andrew

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node
  2020-09-30  5:11 [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Billy Tsai
  2020-09-30  9:06 ` [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region Billy Tsai
@ 2020-10-01  0:36 ` Andrew Jeffery
  2020-10-05  1:55   ` Billy Tsai
  1 sibling, 1 reply; 7+ messages in thread
From: Andrew Jeffery @ 2020-10-01  0:36 UTC (permalink / raw)
  To: Billy Tsai, Rob Herring, Joel Stanley, devicetree,
	linux-arm-kernel, linux-aspeed, linux-kernel
  Cc: BMC-SW

Hi Billy,

On Wed, 30 Sep 2020, at 14:41, Billy Tsai wrote:
> This commit add two sgpiom and two sgpios node into aspeed-g6.dtsi
> and change the register range of gpio0 to fix the hardware design.
> 
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 51 +++++++++++++++++++++++++++++++-
>  1 file changed, 50 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 97ca743363d7..00237daec2a1 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -357,7 +357,7 @@
>  				#gpio-cells = <2>;
>  				gpio-controller;
>  				compatible = "aspeed,ast2600-gpio";
> -				reg = <0x1e780000 0x800>;
> +				reg = <0x1e780000 0x500>;
>  				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>  				gpio-ranges = <&pinctrl 0 0 208>;
>  				ngpios = <208>;
> @@ -365,6 +365,55 @@
>  				interrupt-controller;
>  				#interrupt-cells = <2>;
>  			};
> +			sgpiom0: sgpiom@1e780500 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom";
> +				reg = <0x1e780500 0x100>;
> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <128>;
> +				clocks = <&syscon ASPEED_CLK_APB2>;
> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm1_default>;
> +				status = "disabled";
> +			};
> +
> +			sgpiom1: sgpiom@1e780600 {
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				compatible = "aspeed,ast2600-sgpiom";
> +				reg = <0x1e780600 0x100>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				ngpios = <80>;
> +				clocks = <&syscon ASPEED_CLK_APB2>;
> +				interrupt-controller;
> +				bus-frequency = <12000000>;
> +
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_sgpm2_default>;

Have you tried building this on top of upstream? Because neither sgpm2 nor 
sgps2 are supported by the pinctrl driver. If you have patches that implement 
both mux configurations, can you post them too?

Andrew

^ permalink raw reply	[flat|nested] 7+ messages in thread

* RE: [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region
  2020-10-01  0:32     ` Andrew Jeffery
@ 2020-10-01  1:11       ` Ryan Chen
  0 siblings, 0 replies; 7+ messages in thread
From: Ryan Chen @ 2020-10-01  1:11 UTC (permalink / raw)
  To: Andrew Jeffery, Billy Tsai, Rob Herring, Joel Stanley,
	devicetree, linux-arm-kernel, linux-aspeed, linux-kernel
  Cc: BMC-SW

> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Thursday, October 1, 2020 8:32 AM
> To: Billy Tsai <billy_tsai@aspeedtech.com>; Rob Herring <robh+dt@kernel.org>;
> Joel Stanley <joel@jms.id.au>; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-aspeed@lists.ozlabs.org;
> linux-kernel@vger.kernel.org; Ryan Chen <ryan_chen@aspeedtech.com>
> Cc: BMC-SW <BMC-SW@aspeedtech.com>
> Subject: Re: [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region
> 
> 
> 
> On Thu, 1 Oct 2020, at 09:42, Andrew Jeffery wrote:
> > Hi Billy,
> >
> > On Wed, 30 Sep 2020, at 18:36, Billy Tsai wrote:
> > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > > ---
> > >  arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> > > b/arch/arm/boot/dts/aspeed-g6.dtsi
> > > index 97ca743363d7..b9ec8b579f73 100644
> > > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > > @@ -357,7 +357,7 @@
> > >  				#gpio-cells = <2>;
> > >  				gpio-controller;
> > >  				compatible = "aspeed,ast2600-gpio";
> > > -				reg = <0x1e780000 0x800>;
> > > +				reg = <0x1e780000 0x500>;
> >
> > We took the 0x800 value from the memory space layout table in the
> > datasheet for the 2600. Should that be updated too? Or are you just
> > limiting the region to the registers currently described rather than the
> allocated address space?
> 
> Ah, actually, I see what's going on. We really have this layout (taking some
> liberties):
> 
> 0x1e785000 - 0x1e785500: PGPIO 3.3V
> 0x1e785500 - 0x1e785600: SGPM1
> 0x1e785600 - 0x1e785700: SGPM2
> 0x1e785700 - 0x1e785740: SPGS1
> 0x1e785740 - 0x1e785780: SPGS2
> 0x1e785800 - 0x1e786000: PGPIO 1.8V
> 
> Ryan: Can you change the address space layout table to reflect this? That way it
> still functions as a quick - but accurate - reference.

Yes will resend the patch for update the table. 
0x1e780000 ~ 0x1e780400 PGPIO 3.3V
0x1e780500 - 0x1e780600: SGPM1
0x1e780600 - 0x1e780700: SGPM2
0x1e780700 - 0x1e780740: SPGS1
0x1e780740 - 0x1e780780: SPGS2
0x1e780800 - 0x1e781000: PGPIO 1.8V


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node
  2020-10-01  0:36 ` [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Andrew Jeffery
@ 2020-10-05  1:55   ` Billy Tsai
  0 siblings, 0 replies; 7+ messages in thread
From: Billy Tsai @ 2020-10-05  1:55 UTC (permalink / raw)
  To: Andrew Jeffery, Rob Herring, Joel Stanley, devicetree,
	linux-arm-kernel, linux-aspeed, linux-kernel
  Cc: BMC-SW

Hi Andrew,

On 2020/10/1, 8:36 AM, Andrew Jeffery wrote:

    Hi Billy,
    
    On Wed, 30 Sep 2020, at 14:41, Billy Tsai wrote:
    > This commit add two sgpiom and two sgpios node into aspeed-g6.dtsi
    > and change the register range of gpio0 to fix the hardware design.
    > 
    > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
    > ---
    >  arch/arm/boot/dts/aspeed-g6.dtsi | 51 +++++++++++++++++++++++++++++++-
    >  1 file changed, 50 insertions(+), 1 deletion(-)
    > 
    > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
    > index 97ca743363d7..00237daec2a1 100644
    > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
    > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
    > @@ -357,7 +357,7 @@
    >  				#gpio-cells = <2>;
    >  				gpio-controller;
    >  				compatible = "aspeed,ast2600-gpio";
    > -				reg = <0x1e780000 0x800>;
    > +				reg = <0x1e780000 0x500>;
    >  				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    >  				gpio-ranges = <&pinctrl 0 0 208>;
    >  				ngpios = <208>;
    > @@ -365,6 +365,55 @@
    >  				interrupt-controller;
    >  				#interrupt-cells = <2>;
    >  			};
    > +			sgpiom0: sgpiom@1e780500 {
    > +				#gpio-cells = <2>;
    > +				gpio-controller;
    > +				compatible = "aspeed,ast2600-sgpiom";
    > +				reg = <0x1e780500 0x100>;
    > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
    > +				ngpios = <128>;
    > +				clocks = <&syscon ASPEED_CLK_APB2>;
    > +				interrupt-controller;
    > +				bus-frequency = <12000000>;
    > +
    > +				pinctrl-names = "default";
    > +				pinctrl-0 = <&pinctrl_sgpm1_default>;
    > +				status = "disabled";
    > +			};
    > +
    > +			sgpiom1: sgpiom@1e780600 {
    > +				#gpio-cells = <2>;
    > +				gpio-controller;
    > +				compatible = "aspeed,ast2600-sgpiom";
    > +				reg = <0x1e780600 0x100>;
    > +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
    > +				ngpios = <80>;
    > +				clocks = <&syscon ASPEED_CLK_APB2>;
    > +				interrupt-controller;
    > +				bus-frequency = <12000000>;
    > +
    > +				pinctrl-names = "default";
    > +				pinctrl-0 = <&pinctrl_sgpm2_default>;
    
   > Have you tried building this on top of upstream? Because neither sgpm2 nor 
   > sgps2 are supported by the pinctrl driver. If you have patches that implement 
   > both mux configurations, can you post them too?
    
   > Andrew

Sorry for that.

I will resend another patch which includes pinctrl information to fix this error.
  
Best Regards,
Billy Tsai
 



^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2020-10-05  1:56 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-30  5:11 [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Billy Tsai
2020-09-30  9:06 ` [RESEND PATCH] ARM: dts: aspeed-g6: Fix gpio memory region Billy Tsai
2020-10-01  0:12   ` Andrew Jeffery
2020-10-01  0:32     ` Andrew Jeffery
2020-10-01  1:11       ` Ryan Chen
2020-10-01  0:36 ` [PATCH] ARM: dts: aspeed-g6: Add sgpiom/sgpios node Andrew Jeffery
2020-10-05  1:55   ` Billy Tsai

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).