From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D53E3C4321E for ; Mon, 6 Dec 2021 17:05:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241885AbhLFRIc (ORCPT ); Mon, 6 Dec 2021 12:08:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347520AbhLFQ7P (ORCPT ); Mon, 6 Dec 2021 11:59:15 -0500 Received: from mail-yb1-xb2d.google.com (mail-yb1-xb2d.google.com [IPv6:2607:f8b0:4864:20::b2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D0D7C061746; Mon, 6 Dec 2021 08:55:46 -0800 (PST) Received: by mail-yb1-xb2d.google.com with SMTP id x32so32969185ybi.12; Mon, 06 Dec 2021 08:55:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aptYJVkcFGX1lfiFlH9jb7wZ4NHrgyt69SMZ0ye0woQ=; b=ZeAACAhkLGAxILonk5AKc2T7HT4LX7LvB4WSCZUBpCOGCtr7N9thLbsDZKXHCbFAkl BPwjY1AOgKpMEBVmn3zQpTzXL19EgR/TPRPNTXHKbBrQjhf8//2SBGHupRXXBxpSnB7U FZD68ysh4N7cuVbwl/pxiek3MW5npxrCbsWSY60j+xxws5GSc6SwoKBsnqDF8oNtZZTF ds6LeEDjK9aCrC3trIdMuNnuydekxZ7tNzxsiXx41DEuC85YEOEBytcblkarrtWweyj0 dZlrAJpPZG/4A3YdQ9hp3rOWNCoecaaXtIihrzRHh0dmrAr+s4P49LjyXltFFPToN/kk JKMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aptYJVkcFGX1lfiFlH9jb7wZ4NHrgyt69SMZ0ye0woQ=; b=lpqKCB5SGxuZAVtfjwT+bxvygkdh8EJayqwYZynKbiFHUQiCKXvthntS8s6DCDXL/L F4+8oF2RCalZ2zzq8uXqXTAEFp9R6Rm6KSi/vaeZtFErZj3URONpfRtGfq+91WIn8Jpx tYwIlAx3WeiaRgOkPkGL70mO3nBheTg+hOhzhCEWu0+Fhws7MnssKF9I2luh2Vr9lRhC KdhCcZ6/fcHb/syDZkp+xjHzbxC/vZ4TdhXcANc4boHlJsSEUVrundF2WjwOkdaZOwLk TEFHhmWJtKApYku8+Ox5D2z2/P0IWBUL6S5vcMtxPzdwVYG3J6VFV7v85jZ1bRd/gg5o J3hQ== X-Gm-Message-State: AOAM531K3mF0ochqJIZ5w6F7LxRYo5Tfvk7ZZXyORhQo1kMRp2BODd+z CdA09Srkgx0YB509Y0Ww6Wntzs7XuwDk0GPxj30= X-Google-Smtp-Source: ABdhPJyJmtpWr+FFTHb2pCk3Ovqo7k+sL2iWlIbQthmhvIjWYRMyXsOVfxN7y+xOqPOxPgIcuxUVAUVyLDz9iC7ptAI= X-Received: by 2002:a25:dc4d:: with SMTP id y74mr41725591ybe.422.1638809745426; Mon, 06 Dec 2021 08:55:45 -0800 (PST) MIME-Version: 1.0 References: <20211122103032.517923-1-maz@kernel.org> <8735no70tt.wl-maz@kernel.org> <87tug3clvc.wl-maz@kernel.org> <87r1b7ck40.wl-maz@kernel.org> <87tufvmes9.wl-maz@kernel.org> <87bl21mqwk.wl-maz@kernel.org> <87y24y112a.wl-maz@kernel.org> In-Reply-To: <87y24y112a.wl-maz@kernel.org> From: "Lad, Prabhakar" Date: Mon, 6 Dec 2021 16:55:19 +0000 Message-ID: Subject: Re: [PATCH] of/irq: Add a quirk for controllers with their own definition of interrupt-map To: Marc Zyngier , Rob Herring Cc: Geert Uytterhoeven , Prabhakar Mahadev Lad , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "kernel-team@android.com" , John Crispin , Biwen Li , Chris Brandt , "linux-renesas-soc@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Dec 6, 2021 at 10:26 AM Marc Zyngier wrote: > > On Sun, 05 Dec 2021 22:27:35 +0000, > "Lad, Prabhakar" wrote: > > > > On Wed, Dec 1, 2021 at 4:16 PM Lad, Prabhakar > > wrote: > > > > > > On Wed, Dec 1, 2021 at 2:36 PM Rob Herring wrote: > > > > > > > > On Wed, Dec 1, 2021 at 7:37 AM Lad, Prabhakar > > > > wrote: > > > > > > > > > > Hi Marc/Rob, > > > > > > > > > > On Tue, Nov 30, 2021 at 6:37 PM Marc Zyngier wrote: > > > > > > > > > > > > On Tue, 30 Nov 2021 12:52:21 +0000, > > > > > > "Lad, Prabhakar" wrote: > > > > > > > > > > > > > > On Mon, Nov 29, 2021 at 6:33 PM Rob Herring wrote: > > > > > > > > > > > > > > > > interrupts would work just fine here: > > > > > > > > > > > > > > > > interrupts = , > > > > > > > > , > > > > > > > > , > > > > > > > > , > > > > > > > > , > > > > > > > > , > > > > > > > > , > > > > > > > > ; > > > > > > > > > > > > > > > > We don't need a different solution for N:1 interrupts from N:M. Sure, > > > > > > > > that could become unweldy if there are a lot of interrupts (just like > > > > > > > > interrupt-map), but is that an immediate problem? > > > > > > > > > > > > > > > It's just that with this approach the driver will have to index the > > > > > > > interrupts instead of reading from DT. > > > > > > > > > > > > > > Marc - is it OK with the above approach? > > > > > > > > > > > > Anything that uses standard properties in a standard way works for me. > > > > > > > > > > > I added interrupts property now instead of interrupt-map as below: > > > > > > > > > > irqc: interrupt-controller@110a0000 { > > > > > compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; > > > > > #address-cells = <0>; > > > > > interrupt-parent = <&gic>; > > > > > interrupt-controller; > > > > > reg = <0 0x110a0000 0 0x10000>; > > > > > interrupts = > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > , > > > > > ; > > > > > clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, > > > > > <&cpg CPG_MOD R9A07G044_IA55_PCLK>; > > > > > clock-names = "clk", "pclk"; > > > > > power-domains = <&cpg>; > > > > > resets = <&cpg R9A07G044_IA55_RESETN>; > > > > > }; > > > > > > > > > > > > > > > In the hierarchal interrupt code its parsed as below: > > > > > on probe fetch the details: > > > > > range = of_get_property(np, "interrupts", &len); > > > > > if (!range) > > > > > return -EINVAL; > > > > > > > > > > for (len /= sizeof(*range), j = 0; len >= 3; len -= 3) { > > > > > if (j >= IRQC_NUM_IRQ) > > > > > return -EINVAL; > > > > > > > > > > priv->map[j].args[0] = be32_to_cpu(*range++); > > > > > priv->map[j].args[1] = be32_to_cpu(*range++); > > > > > priv->map[j].args[2] = be32_to_cpu(*range++); > > > > > priv->map[j].args_count = 3; > > > > > j++; > > > > > > > > Not sure what's wrong, but you shouldn't be doing your own parsing. > > > > The setup shouldn't look much different than a GPIO controller > > > > interrupts except you have multiple parent interrupts. > > > > > > > Sorry does that mean the IRQ domain should be chained handler and not > > > hierarchical? Or is it I have miss-understood. > > I guess the core DT code allocates the interrupts itself, as if the > interrupt controller was the interrupt producer itself (which isn't > the case here), bypassing the hierarchical setup altogether. > > We solved it on the MSI side by not using 'interrupts'. Either we > adopt a similar solution for wired interrupts, or we fix the core DT > code. > So maybe for now we go with your earlier suggestion of using "interrupt-range"? (And address the core DT in near future) Rob, is that OK with you? Cheers, Prabhakar > > > > > > If the IRQ domain has to be hierarchical how do we map to the parent? > > > (based on the previous reviews Marc had suggested to implement as > > > hierarchical [1]) > > > > > Gentle ping. > > Please move this discussion to the relevant thread. > > M. > > -- > Without deviation from the norm, progress is not possible.