From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C267CC55178 for ; Fri, 30 Oct 2020 09:10:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66A4620725 for ; Fri, 30 Oct 2020 09:10:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="eSDiZBsd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725790AbgJ3JKA (ORCPT ); Fri, 30 Oct 2020 05:10:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726319AbgJ3JJ5 (ORCPT ); Fri, 30 Oct 2020 05:09:57 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66D5FC0613D2 for ; Fri, 30 Oct 2020 02:09:56 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id g12so5575925wrp.10 for ; Fri, 30 Oct 2020 02:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bfUnFTOfSXFG25x3BnIgOzcDN4IPlLEtsgB9WMJzOuA=; b=eSDiZBsdVeZ8YhjpBNK5ZgQZWSgQI5Mysm8lQ5TsGB2ZqMUdGhEFIZP0VVXlfMcKUm LwPd8O3SIgi+6vu/tXHEeeU5K9mHbQELrYgErcweripmTqaSfkaydOeJidaFvanXfJF2 8NsNV450bLQ0tB+LEYEGZIkv3HbBIQr4uUz9AT3g7vq97ZJtf/SbHZk/vpqr1f0nSmmh RzYdh3Yli3/CeK2CMtGvCgC50qQAT7iXmNNKrUEa0VVC3fDCR7zFXvsl7GFmDapfrU2W LRzQo9BWPe95GLGk0Mur0lzUE7SqBeACwPzrbqLJ8ONVm2cUNvOj1miLDmYYNjlcSxK+ FNUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bfUnFTOfSXFG25x3BnIgOzcDN4IPlLEtsgB9WMJzOuA=; b=Udf5bwYtYK5QN+jk5Ysr+Iw2YxQmeB/9y3s1cdfHX1wG4ZaGY8SnWGd7IxgE2ImZGi 0iMTJO1offRku6NDVB4ruyYZbjx/LGzcpWE+jw6btqrbynOjVH06C1vhQJdCgTHuoD7V oMtCJo2DDTdJZVbNZXFtJjd8bcy/D7GjLk1jETklhhhNhIra6fuS/EZYcKpPKocivC3K qcMz0cjCYxKgiMZ6LStr3kd/8QzPZy9/Y9vi6LMApxfxeAN0ooaUEWXA73WINsfaMUFl gDDqBb6hJJUHKqQR7Q5K3mVaD5216wBYK4y2qJDysQ9xuaYIL4pHcQFtoxx33NfWGRaC Fqhg== X-Gm-Message-State: AOAM531O1S8nK/kuLadlU04IkSHH1slCXRESsNjnNumqTPNqcj3AAVhe LV1UASo1qB0el7Hf7rWgblmqZgeu0o15rWXya8ihWw== X-Google-Smtp-Source: ABdhPJyA9i/Zk/3TmJNQX1c4BPqrlSQfKCOiUmrNfi7O3zDzfW1MV/RUDeOTVF3R3BgHfJ1Qhnt5xSnKRxgMdqlarFM= X-Received: by 2002:a5d:6681:: with SMTP id l1mr1797680wru.356.1604048995074; Fri, 30 Oct 2020 02:09:55 -0700 (PDT) MIME-Version: 1.0 References: <20201028232759.1928479-1-atish.patra@wdc.com> <20201028232759.1928479-4-atish.patra@wdc.com> In-Reply-To: <20201028232759.1928479-4-atish.patra@wdc.com> From: Anup Patel Date: Fri, 30 Oct 2020 14:39:43 +0530 Message-ID: Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC To: Atish Patra Cc: "linux-kernel@vger.kernel.org List" , Albert Ou , Alistair Francis , Anup Patel , devicetree@vger.kernel.org, linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring , Padmarao Begari , Daire McNamara , Cyril.Jean@microchip.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote: > > Enable Microchip PolarFire ICICLE soc config in defconfig. > It allows the default upstream kernel to boot on PolarFire ICICLE board. > > Signed-off-by: Atish Patra > --- > arch/riscv/configs/defconfig | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index d222d353d86d..2660fa05451e 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -16,6 +16,7 @@ CONFIG_EXPERT=y > CONFIG_BPF_SYSCALL=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > +CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SMP=y > CONFIG_JUMP_LABEL=y > CONFIG_MODULES=y > @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y > CONFIG_USB_OHCI_HCD_PLATFORM=y > CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > +CONFIG_SDHCI=y > +CONFIG_MMC_SDHCI_PLTFM=y > +CONFIG_MMC_SDHCI_CADENCE=y > CONFIG_MMC=y > CONFIG_MMC_SPI=y > CONFIG_RTC_CLASS=y > -- > 2.25.1 > Looks good to me. Reviewed-by: Anup Patel Regards, Anup