From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D391AC4338F for ; Mon, 26 Jul 2021 12:45:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B72A660F45 for ; Mon, 26 Jul 2021 12:45:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234074AbhGZMFO (ORCPT ); Mon, 26 Jul 2021 08:05:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233754AbhGZMFG (ORCPT ); Mon, 26 Jul 2021 08:05:06 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88DC0C061757 for ; Mon, 26 Jul 2021 05:45:35 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id p5so5816474wro.7 for ; Mon, 26 Jul 2021 05:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EdSEiQhPPfqlW+mNBlXL/6LkyvS46s9MWaLUDSXboLs=; b=cMAiwG60O3mJ/yFl82iRKWkX/2RsxNQFV+GdGrduhGDtDa2s1/iXKKFhmMPpVGXPLK fJa7sibt5Qn1sSJM14MEXSKYhHVIGjDRCz9X7aNrg6dOmwXXmwEQFDbWwzXzywuwj+VD xwc6C5GLLOEluhgH8wwnqHv/dEwyGGZ0xX8MMn40qeZre05Pcv5x9J8Ez3DbQM6BS2ks mGLPEPyxshCEpdnYQ3lZIzNETd8SIBde/3rhDmD0DG54cIbOK2eUcfRrJtwG/myAkFrz nQ3d6EkT5soST7X/ajaFq1FVf5YxMeCPk9mlcbPCYTVcru1CUnGpvdLskrzEKpqQ0k3x wpiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EdSEiQhPPfqlW+mNBlXL/6LkyvS46s9MWaLUDSXboLs=; b=c7vU3JrCByCXDVc23mR/8TGnkLkB/2VALlttGOP3jGAGQQhiwQsc13MHsY2IVe0EF9 5syEhtQiFFvuBIcLw6dBCrTm1rhzUAzTdhE1OU/J9nocbMKA7I1vAkxLZQPCSsgSzAP0 WzSGmTk/v0BM1sNJD1i0mtLUmIbJlU2mFw+41CAZgrXh1YuMO3TG19PU/RWuytpK6Y0L OLKGHLj3eyC4bqnzyu0atjRiSfULi1WlL0ncghayeFtpC2CbjlabBCT4vhvvohUra7qJ eksKULzcxx+YWtZCbeQcIIM+TG6TObyQiWeMZuwhumlHCaQN7lAiiXCOOJ/LuMVGGBys hqAw== X-Gm-Message-State: AOAM532RL2F140zoBxJUWTE+dPhuDLCKlEeeCLrxOqpF/DnC9l8i/RMs UI0rJ1i6c5EgOaiEzT9DC7c7RmmwUqlf1GkyO8GpBQ== X-Google-Smtp-Source: ABdhPJwkUJfUzY+D0ZUeN/xa+//W784LaiFLRerJU1kMI4d9SXUSL+tAmGatjZAFWSLpWKG5op/x6x/WbN6LfRBY86I= X-Received: by 2002:a05:6000:2a1:: with SMTP id l1mr18569977wry.128.1627303534054; Mon, 26 Jul 2021 05:45:34 -0700 (PDT) MIME-Version: 1.0 References: <20210618123851.1344518-1-anup.patel@wdc.com> In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> From: Anup Patel Date: Mon, 26 Jul 2021 18:15:20 +0530 Message-ID: Subject: Re: [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support To: Marc Zyngier Cc: Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Rob Herring , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , DTML , Anup Patel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Marc, I have taken the approach of IPI domains (like you suggested) in this series. What do you think ? Regards, Anup On Fri, Jun 18, 2021 at 6:09 PM Anup Patel wrote: > > Most of the existing RISC-V platforms use SiFive CLINT to provide M-level > timer and IPI support whereas S-level uses SBI calls for timer and IPI > support. Also, the SiFive CLINT device is a single device providing both > timer and IPI functionality so RISC-V platforms can't partially implement > SiFive CLINT device and provide alternate mechanism for timer and IPI. > > The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the > limitations of SiFive CLINT by: > 1) Taking modular approach and defining timer and IPI functionality as > separate devices so that RISC-V platforms can include only required > devices > 2) Providing dedicated MMIO device for S-level IPIs so that SBI calls > can be avoided for IPIs in Linux RISC-V > 3) Allowing multiple instances of timer and IPI devices for a > multi-socket (or multi-die) NUMA systems > 4) Being backward compatible to SiFive CLINT so that existing RISC-V > platforms stay compliant with RISC-V ACLINT specification > > Latest RISC-V ACLINT specification (will be frozen in a month) can be > found at: > https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > > This series adds RISC-V ACLINT support and can be found in riscv_aclint_v2 > branch at: > https://github.com/avpatel/linux > > To test this series, the RISC-V ACLINT support for QEMU and OpenSBI > can be found in the riscv_aclint_v1 branch at: > https://github.com/avpatel/qemu > https://github.com/avpatel/opensbi > > Changes since v1: > - Added a new PATCH3 to treat IPIs as normal Linux IRQs for RISC-V kernel > - New SBI IPI call based irqchip driver in PATCH3 which is only initialized > by riscv_ipi_setup() when no Linux IRQ numbers are available for IPIs > - Moved DT bindings patches before corresponding driver patches > - Implemented ACLINT SWI driver as a irqchip driver in PATCH7 > - Minor nit fixes pointed by Bin Meng > > Anup Patel (11): > RISC-V: Clear SIP bit only when using SBI IPI operations > RISC-V: Use common print prefix in smp.c > RISC-V: Treat IPIs as normal Linux IRQs > RISC-V: Allow marking IPIs as suitable for remote FENCEs > RISC-V: Use IPIs for remote TLB flush when possible > dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings > irqchip: Add ACLINT software interrupt driver > RISC-V: Select ACLINT SWI driver for virt machine > dt-bindings: timer: Add ACLINT MTIMER bindings > clocksource: clint: Add support for ACLINT MTIMER device > MAINTAINERS: Add entry for RISC-V ACLINT drivers > > .../riscv,aclint-swi.yaml | 82 ++++++ > .../bindings/timer/riscv,aclint-mtimer.yaml | 55 ++++ > MAINTAINERS | 9 + > arch/riscv/Kconfig | 1 + > arch/riscv/Kconfig.socs | 1 + > arch/riscv/include/asm/sbi.h | 2 + > arch/riscv/include/asm/smp.h | 48 +++- > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/cpu-hotplug.c | 2 + > arch/riscv/kernel/irq.c | 1 + > arch/riscv/kernel/sbi-ipi.c | 223 ++++++++++++++ > arch/riscv/kernel/sbi.c | 15 - > arch/riscv/kernel/smp.c | 171 +++++------ > arch/riscv/kernel/smpboot.c | 4 +- > arch/riscv/mm/tlbflush.c | 62 +++- > drivers/clocksource/timer-clint.c | 58 ++-- > drivers/irqchip/Kconfig | 11 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-aclint-swi.c | 271 ++++++++++++++++++ > drivers/irqchip/irq-riscv-intc.c | 55 ++-- > 20 files changed, 879 insertions(+), 194 deletions(-) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml > create mode 100644 arch/riscv/kernel/sbi-ipi.c > create mode 100644 drivers/irqchip/irq-aclint-swi.c > > -- > 2.25.1 >