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[209.85.222.54]) by smtp.gmail.com with ESMTPSA id g140sm3088071vkf.18.2020.01.31.13.43.17 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 31 Jan 2020 13:43:17 -0800 (PST) Received: by mail-ua1-f54.google.com with SMTP id z24so3138075uam.7 for ; Fri, 31 Jan 2020 13:43:17 -0800 (PST) X-Received: by 2002:ab0:724c:: with SMTP id d12mr7797680uap.0.1580506997224; Fri, 31 Jan 2020 13:43:17 -0800 (PST) MIME-Version: 1.0 References: <1580472220-3453-1-git-send-email-smasetty@codeaurora.org> <1580472220-3453-2-git-send-email-smasetty@codeaurora.org> In-Reply-To: <1580472220-3453-2-git-send-email-smasetty@codeaurora.org> From: Doug Anderson Date: Fri, 31 Jan 2020 13:43:06 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob To: Sharat Masetty Cc: freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dri-devel@freedesktop.org, linux-arm-msm , LKML , Bjorn Andersson , Jordan Crouse , Matthias Kaehlcke Content-Type: text/plain; charset="UTF-8" Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, On Fri, Jan 31, 2020 at 4:04 AM Sharat Masetty wrote: > > + adreno_smmu: iommu@5040000 { > + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; > + reg = <0 0x05040000 0 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>; > + > + clock-names = "bus", "iface", "mem_iface_clk"; Repeated comment from v2 feedback: Please send a patch to: Documentation/devicetree/bindings/iommu/arm,smmu.yaml ...adding 'qcom,sc7180-smmu-v2'. If you do this it will point out that you've added a new clock: "mem_iface_clk". Is this truly a new clock in sc7180 compared to previous IOMMUs? ...or is it not really needed? > + gmu: gmu@506a000 { > + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; > + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, > + <0 0x0b490000 0 0x10000>; > + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; > + clock-names = "gmu", "cxo", "axi", "memnoc"; > + power-domains = <&gpucc CX_GDSC>; > + power-domain-names = "cx"; As per continued comments on v2, please see if this works for you: power-domains = <&gpucc CX_GDSC>, <0>; power-domain-names = "cx", "gx"; ...and work to get something more real for "gx" ASAP. It did seem to boot for me and (unless someone disagrees) it seems better than totally leaving it out / violating the bindings? -Doug