From mboxrd@z Thu Jan 1 00:00:00 1970 From: Greentime Hu Subject: Re: [PATCH v2 25/35] nds32: Build infrastructure Date: Thu, 30 Nov 2017 17:29:27 +0800 Message-ID: References: <5e1be9ebc591c6de79b75f726a5a38b2564eaa92.1511785528.git.green.hu@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: Sender: netdev-owner@vger.kernel.org To: Geert Uytterhoeven Cc: Arnd Bergmann , Greentime , Linux Kernel Mailing List , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Networking , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , "linux-serial@vger.kernel.org" , Vincent Chen List-Id: devicetree@vger.kernel.org 2017-11-30 15:52 GMT+08:00 Geert Uytterhoeven : > On Thu, Nov 30, 2017 at 6:48 AM, Greentime Hu wrote: >> 2017-11-30 4:27 GMT+08:00 Arnd Bergmann : >>> On Wed, Nov 29, 2017 at 3:10 PM, Greentime Hu wrote: >>>> 2017-11-29 19:57 GMT+08:00 Arnd Bergmann : >>>>> On Wed, Nov 29, 2017 at 12:39 PM, Greentime Hu wrote: >> I think I can use this name "CPU_V3" for all nds32 v3 compatible cpu. >> It will be implemented like this. >> >> config HWZOL >> bool "hardware zero overhead loop support" >> depends on CPU_D10 || CPU_D15 >> default n >> help >> A set of Zero-Overhead Loop mechanism is provided to reduce the >> instruction fetch and execution overhead of loop-control instructions. >> It will save 3 registers($LB, $LC, $LE) for context saving if say Y. >> You don't need to save these registers if you can make sure your user >> program doesn't use these registers. >> >> If unsure, say N. >> >> config CPU_CACHE_NONALIASING >> bool "Non-aliasing cache" >> depends on !CPU_N10 && !CPU_D10 >> default n >> help >> If this CPU is using VIPT data cache and its cache way size is larger >> than page size, say N. If it is using PIPT data cache, say Y. >> >> If unsure, say N. > > I still think it will be easier to revert the logic, and have > CPU_CACHE_ALIASING. > Thanks Geert I will implement it like this. config HWZOL bool "hardware zero overhead loop support" depends on CPU_D10 || CPU_D15 default n help A set of Zero-Overhead Loop mechanism is provided to reduce the instruction fetch and execution overhead of loop-control instructions. It will save 3 registers($LB, $LC, $LE) for context saving if say Y. You don't need to save these registers if you can make sure your user program doesn't use these registers. If unsure, say N. config CPU_CACHE_ALIASING bool "Aliasing cache" depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3 default y help If this CPU is using VIPT data cache and its cache way size is larger than page size, say Y. If it is using PIPT data cache, say N. If unsure, say Y. choice prompt "CPU type" default CPU_V3 config CPU_N15 bool "AndesCore N15" config CPU_N13 bool "AndesCore N13" select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB config CPU_N10 bool "AndesCore N10" select CPU_CACHE_ALIASING config CPU_D15 bool "AndesCore D15" config CPU_D10 bool "AndesCore D10" select CPU_CACHE_ALIASING config CPU_V3 bool "AndesCore v3 compatible" select ANDES_PAGE_SIZE_8KB endchoice