From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90859C4646C for ; Thu, 1 Apr 2021 17:43:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B0F361399 for ; Thu, 1 Apr 2021 17:43:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234831AbhDARnC (ORCPT ); Thu, 1 Apr 2021 13:43:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234641AbhDARil (ORCPT ); Thu, 1 Apr 2021 13:38:41 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B5C0C0610D4 for ; Thu, 1 Apr 2021 05:33:59 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id t140so1396239pgb.13 for ; Thu, 01 Apr 2021 05:33:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EsqA9Xv1llCUvLw8edrdaV5ZoeKuJnc13OOMvfzSgxY=; b=HvEMU+9tQn1GkFvgVgNpDGEMAtzN3iWIIpIqpjHnH3PuIQx/41BH4FPhlsrxmzJ7B8 L2ALnq3tSypyjY5/I2dj+e7l2fmL2+pioKtbUoAHVuat+G7R/l0ATYHxFN3e0HYVKZ3N X1KRmPPuu+zjjTXiovmOa6heMHJcGPRPsUrrU/c+ic0Tew8Dk/4lDGWHd8bcswuBcB9K fG85AyStYAbSqXDb5FHrCg6IrLsMpA92c/Cj927Tkg/YZ3ETIp4iRUIQGTj1yiEllcW+ fepykwK5q6/UsV9VB3RqNAxZZxkkNuKoyG9wmDf/2PiEeesDmmNmV4qw0GUKKYmnzISi 168g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EsqA9Xv1llCUvLw8edrdaV5ZoeKuJnc13OOMvfzSgxY=; b=ZDGmn/M+bxt2xXqfmvruDmV9oq53TlfQsA132w4mpRiyGc1+LDVUNDuIi4xMkAjbZ5 bIxrLwXFJc43X9nOoPQnU29PqUTUCPf37DdYQxWHSd3WpEdaDh0nKKfocx5vmjuuQu9n mTINLfUIOGw8tOGmsv3cg4men8FYuExQ/AX1gZXyZ4afFw5EYFJum69ntYXivIPuvjlP u54OTD/8UnlFqNcCcGFz0qaqThOTfDx9C3kZ0XjP8aiZKZuJWT1q/rg8ZF+g6f1vqHVE B67GMR5JGjPxQcMs0mfnWhl+mxBZ2R9/UJhLQ0gkVcOfWObNMP7IQqdW9DeIckqmEz35 rJyw== X-Gm-Message-State: AOAM530l6AlgGNCz5py9KqBBh9h9I8N5j5V2mwsc2C7lzNyGp8F/HM+v 0sD7JBI0wX824LypCYEqgEToDcmOOLjKg7wfb1hYqw== X-Google-Smtp-Source: ABdhPJyaGyv5cIOFak7z5jWf50xKVPz9OGnuR20y6+iAsqhPnXNOISrhs8/7nH+WsYv0DxswgJgz0ro4GehSANLiKgw= X-Received: by 2002:a62:80cf:0:b029:1f3:1959:2e42 with SMTP id j198-20020a6280cf0000b02901f319592e42mr7324814pfd.39.1617280439001; Thu, 01 Apr 2021 05:33:59 -0700 (PDT) MIME-Version: 1.0 References: <4b09b40ce53c5b5fe7d2ba65a3c7a1b23f6eec04.1616135353.git.xji@analogixsemi.com> <20210324075108.GA1466804@anxtwsw-Precision-3640-Tower> In-Reply-To: <20210324075108.GA1466804@anxtwsw-Precision-3640-Tower> From: Robert Foss Date: Thu, 1 Apr 2021 14:33:47 +0200 Message-ID: Subject: Re: [PATCH v6 1/5] dt-bindings:drm/bridge:anx7625:add vendor define flags To: Xin Ji Cc: Laurent Pinchart , Rob Herring , David Airlie , Nicolas Boichat , Hsin-Yi Wang , Daniel Vetter , Sam Ravnborg , Laurent Pinchart , Maxime Ripard , Mark Brown , =?UTF-8?Q?Ricardo_Ca=C3=B1uelo?= , dri-devel , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Bernie Liang , Sheng Pan , Zhen Li , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hey Xin, This series no longer applies to drm-misc/drm-misc-next, please rebase it. On Wed, 24 Mar 2021 at 08:52, Xin Ji wrote: > > On Sun, Mar 21, 2021 at 02:00:38PM +0200, Laurent Pinchart wrote: > > Hi Xin, > > > > Thank you for the patch. > > > > On Fri, Mar 19, 2021 at 02:32:39PM +0800, Xin Ji wrote: > > > Add 'bus-type' and 'data-lanes' define for port0. Define DP tx lane0, > > > lane1 swing register array define, and audio enable flag. > > > > > > Signed-off-by: Xin Ji > > > --- > > > .../display/bridge/analogix,anx7625.yaml | 58 ++++++++++++++++++- > > > 1 file changed, 57 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > > index c789784efe30..3f54d5876982 100644 > > > --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > > +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml > > > @@ -34,6 +34,26 @@ properties: > > > description: used for reset chip control, RESET_N pin B7. > > > maxItems: 1 > > > > > > + analogix,lane0-swing: > > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > > + minItems: 1 > > > + maxItems: 20 > > > + description: > > > + an array of swing register setting for DP tx lane0 PHY, please don't > > > + add this property, or contact vendor. > > > > DT properties need to be documented. Contacting the vendor doesn't count > > as documentation I'm afraid. > > Hi Laurent Pinchart, thanks for your comment. For the DP phy swing > setting, it is hard to describe in here, needs to refer the anx7625 > datasheet and programming guide. Basically, no need to change the DP phy > swing setting. > Laurent is right. But if the value practically is a constant, you can move the swing register into the driver. It should still be documented as well as possible, but we can be a little bit more flexible. > > > @@ -73,6 +123,10 @@ examples: > > > enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; > > > reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; > > > > > > + analogix,audio-enable; > > > + analogix,lane0-swing = <0x14 0x54 0x64 0x74 0x29 0x7b 0x77 0x5b>; > > > + analogix,lane1-swing = <0x14 0x54 0x64 0x74 0x29 0x7b 0x77 0x5b>; > > > + > > > ports { > > > #address-cells = <1>; > > > #size-cells = <0>;