From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
LKML <linux-kernel@vger.kernel.org>,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 09/22] clk: mediatek: Add MT8195 imgsys clock support
Date: Tue, 6 Jul 2021 17:07:09 +0800 [thread overview]
Message-ID: <CAGXv+5F0hTL2Meafo6cQ4FaAMkU+nRZBcnLgeXOgrHAttrNkBQ@mail.gmail.com> (raw)
In-Reply-To: <20210616224743.5109-10-chun-jie.chen@mediatek.com>
Hi,
On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 imgsys clock providers
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 6 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8195-img.c | 98 +++++++++++++++++++++++++++
> 3 files changed, 105 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-img.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 6a6e496d08a4..f92d0b6b7eec 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -612,6 +612,12 @@ config COMMON_CLK_MT8195_CCUSYS
> help
> This driver supports MediaTek MT8195 ccusys clocks.
>
> +config COMMON_CLK_MT8195_IMGSYS
> + bool "Clock driver for MediaTek MT8195 imgsys"
> + depends on COMMON_CLK_MT8195
> + help
> + This driver supports MediaTek MT8195 imgsys clocks.
> +
> config COMMON_CLK_MT8516
> bool "Clock driver for MediaTek MT8516"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index bb8aac6f9185..1768eda917c2 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -85,5 +85,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS) += clk-mt8195-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8195_AUDSYS_SRC) += clk-mt8195-aud_src.o
> obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o
> obj-$(CONFIG_COMMON_CLK_MT8195_CCUSYS) += clk-mt8195-ccu.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c
> new file mode 100644
> index 000000000000..923fa82aedae
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-img.c
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs img_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_IMG(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate img_clks[] = {
> + GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img_sel", 0),
> + GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "img_sel", 1),
> + GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "img_sel", 2),
> + GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "img_sel", 3),
> + GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "img_sel", 4),
> + GATE_IMG(CLK_IMG_DIP0, "img_dip0", "img_sel", 8),
> + GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "img_sel", 9),
> + GATE_IMG(CLK_IMG_IPE, "img_ipe", "img_sel", 10),
> + GATE_IMG(CLK_IMG_DIP1, "img_dip1", "img_sel", 11),
> + GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "img_sel", 12),
> + GATE_IMG(CLK_IMG_GALS, "img_gals", "img_sel", 31),
> +};
> +
> +static const struct mtk_gate img1_dip_top_clks[] = {
> + GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "img_sel", 0),
> + GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "img_sel", 1),
> +};
> +
> +static const struct mtk_gate img1_dip_nr_clks[] = {
> + GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "img_sel", 0),
Adding a clock for a bit that is named "reserved" is sort of weird.
Does it actually exist and function?
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
next prev parent reply other threads:[~2021-07-06 9:07 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-06-24 21:21 ` Rob Herring
2021-07-12 9:32 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-06-24 21:22 ` Rob Herring
2021-07-12 9:37 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:43 ` Matthias Brugger
2021-07-01 4:02 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
2021-07-02 11:44 ` Chen-Yu Tsai
[not found] ` <1626913060.1546.4.camel@mtksdaap41>
2021-07-22 7:44 ` Chen-Yu Tsai
2021-08-11 4:31 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 7:06 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
2021-07-05 10:07 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-07-06 8:53 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-07-06 9:00 ` Chen-Yu Tsai
2021-08-17 0:56 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-07-06 9:07 ` Chen-Yu Tsai [this message]
2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-07-06 9:11 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-07-09 6:29 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-07-09 6:39 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
2021-07-09 8:24 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-12 1:34 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-07-09 8:51 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-07-09 9:30 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-07-09 10:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-07-09 10:38 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-07-09 10:45 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-07-12 8:34 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-07-12 8:51 ` Chen-Yu Tsai
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