From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C457C11F65 for ; Wed, 30 Jun 2021 11:09:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F9616140F for ; Wed, 30 Jun 2021 11:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234161AbhF3LMW (ORCPT ); Wed, 30 Jun 2021 07:12:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229882AbhF3LMW (ORCPT ); Wed, 30 Jun 2021 07:12:22 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5884AC061756 for ; Wed, 30 Jun 2021 04:09:53 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id u20so2687338ljo.12 for ; Wed, 30 Jun 2021 04:09:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Rm4+AwW3LWH2YQHGgTfNo9gJL+afdzfJtfRIoJfvAJc=; b=IE4nSEae0+ZNPzwJoKlwld0IYMdDWkixjHhLI3tUBqdFmS+a6KK5cYvjzyrNiwZmdF Z0m6eXqZtwFMVuQd3GrlSzs2UcjhKOZHgP0a2+UvPrLvGf6REbtdTFZU1RZeiK+YMpi+ XfOkbN6NpLc+GUcqYnxdCqJta/t/pBzt1xKP0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Rm4+AwW3LWH2YQHGgTfNo9gJL+afdzfJtfRIoJfvAJc=; b=TP2NLggMW3476iCuaQi9MfQOaW7orX6MQtdkw/uj3CLbcocHh6TUfFoy4QkFoke879 uOP47ePHaO0b4yzXsCxkJC2Yju4RSLEZ2ebIw3sGFmfvK8z/AJrJ2c+KdjIYBw2Gu+5N em1372qKB8kvDuadAIhH7ta5V/0i9r0I+A2pnCefH93EQnA1/QeAo2e98NezpFY4rl1S TG/Fnn1ODeQlGo5xKB//mHPX3EOED8+3j4eK3rQVLoHG97ZXZgFK1mMq4Hir9f8jeF0l WGHfX0prVQhBAF6OgmFkYG6j3/M9KatyOuyjdcKy6TlHdS75pkfBcp7ifM7lPMpusi/k WQmg== X-Gm-Message-State: AOAM533rpzRQPfqdOv4Am1R62l9GS+wj6c1eXZy+HTFSeguchePLvJt+ yakY+0DVVdNfcfD+3DmsfNnz3VN95+9/3VzmIYW4jA== X-Google-Smtp-Source: ABdhPJzHKuADQa+MobKZ58Bk27asyyFyPDlClM32paRLGxROtq0/z4kqJ9wzvBtX+VJ0lDLBPbqJCGectO03IhUHOfg= X-Received: by 2002:a05:651c:32e:: with SMTP id b14mr7332089ljp.251.1625051391558; Wed, 30 Jun 2021 04:09:51 -0700 (PDT) MIME-Version: 1.0 References: <20210616224743.5109-1-chun-jie.chen@mediatek.com> <20210616224743.5109-4-chun-jie.chen@mediatek.com> In-Reply-To: From: Chen-Yu Tsai Date: Wed, 30 Jun 2021 19:09:40 +0800 Message-ID: Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg To: Matthias Brugger Cc: Chun-Jie Chen , Stephen Boyd , Nicolas Boichat , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger wrote: > > > > On 30/06/2021 09:31, Chen-Yu Tsai wrote: > > On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen > > wrote: > >> > >> On MT8195, tuner_en_reg is moved to register offest 0x0. > >> If we only judge by tuner_en_reg, it may lead to wrong address. > >> Add tuner_en_bit to the check condition. And it has been confirmed, > >> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by > >> clock square control. > >> > >> Signed-off-by: Chun-Jie Chen > > > > Reviewed-by: Chen-Yu Tsai > > > > Though you might want to consider converting these types of checks into feature > > flags. > > > > Yes I think adding a feature flag is the way to go. Luckily there are only a few > SoCs that will need updates at the same time. I also see that the different clock modules are tied together using only clock names written in the drivers, instead of clock references in the device tree. Unfortunately reworking this would likely require a lot more work. I previously did a bit of internal reworking for the sunxi drivers. While not the same, I think the plumbing required is comparable. ChenYu