From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 077E4C4363A for ; Fri, 23 Oct 2020 13:22:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6374208FE for ; Fri, 23 Oct 2020 13:22:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Vc/aFalK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S373082AbgJWNW1 (ORCPT ); Fri, 23 Oct 2020 09:22:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S372993AbgJWNW0 (ORCPT ); Fri, 23 Oct 2020 09:22:26 -0400 Received: from mail-io1-xd42.google.com (mail-io1-xd42.google.com [IPv6:2607:f8b0:4864:20::d42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4654AC0613CE for ; Fri, 23 Oct 2020 06:22:26 -0700 (PDT) Received: by mail-io1-xd42.google.com with SMTP id h21so1721043iob.10 for ; Fri, 23 Oct 2020 06:22:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=dEfyHhDfb1J29xg/MU/EbZi3PKtT0a0IQvdwghsKDtI=; b=Vc/aFalK0DvJiQJ6eLeXvAn2o0DkQ8Qxaxf/zkJ5i2Bd96A0iYtOr7kB/0ZxTICBTM bBbkf0g+hg2FsFBqDOJn2surMyMRVdGvI8SlpsxBqLHPB0bTBXQCYAADAMe8AY+sPfPV UG4foWoJHsMcJKLtlJanUv/iidgqfXPw3srC0Ky1+jCl44RoSu96dBj9cpf8fR38C/VT llJp+YOmTpvqzaGWxhxG7SaO28a03BR094hhhCBqw4gRwIn8qqXsuyNkuc4NHWntm1y4 o+k85ReMGp0MbwIiH+rvgW4rRHUPI5RKVwXyHIUx1M0Ar7DIh/HICBBU8NxvXYFlsLuc 7lRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dEfyHhDfb1J29xg/MU/EbZi3PKtT0a0IQvdwghsKDtI=; b=rRAAprGVx+CJtvp58TDlNDnDSiuaU7q4TR3VIk/AiAthZL6u7NYxC+Rky2WwSKEcNE rgPenjS4KgQEFqEHWfgadhLr//mmSjle7McJgLxr5i4Y2p6hQrObLNdc2KfKyotITT+0 UFe4U6I5a5FieWPpqpL0dxns70H0f8lbrsk7F665lV06b7tYDxRH7L8LFOMcYUkS6hiD +ITVO7StvAQJj8qilTGsbXbydS4DyH5L7ts4MdOmPrFa8aYVP25Z1dKpUD8NHfb9tLo6 Jl4BmiQZdtmtSkmxxNa0jCzr8tnAZneF7hN9SdTPX1yot8amu/GXYUJRXPI+PHV7XYoS NiYA== X-Gm-Message-State: AOAM532gKc7Yv9uJMbNHHWoKMBbGg9tCY03gdrTz/MgtP2KvH1Md1591 Qzu5/jNOQxGTVW+64R0erve6eS15mSYHY/Yb680= X-Google-Smtp-Source: ABdhPJy2fko2aHVOryqMcDa9xZgBaE00yQwIZgXNGqGaE5aGhoB8VmbGSoN37geh18VjLVStPLxefNtpzzHRHjtmGyU= X-Received: by 2002:a5e:de0b:: with SMTP id e11mr1501416iok.92.1603459345364; Fri, 23 Oct 2020 06:22:25 -0700 (PDT) MIME-Version: 1.0 References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-11-l.stach@pengutronix.de> In-Reply-To: <20200930155006.535712-11-l.stach@pengutronix.de> From: Adam Ford Date: Fri, 23 Oct 2020 08:22:14 -0500 Message-ID: Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power domains To: Lucas Stach Cc: Shawn Guo , Rob Herring , Marek Vasut , devicetree , Frieder Schrempf , patchwork-lst@pengutronix.de, NXP Linux Team , Sascha Hauer , Fabio Estevam , arm-soc Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Sep 30, 2020 at 10:55 AM Lucas Stach wrote: > > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. > > Signed-off-by: Lucas Stach > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 76f040e4be5e..a841fb2d0458 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -4,6 +4,8 @@ > */ > > #include > +#include > +#include > #include > #include > #include > @@ -547,6 +549,61 @@ > interrupts = ; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; Does this need an interrupt index within the GIC? possibly something like: interrupts = ; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > + }; > + > + pgc_pcie: power-domain@1 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg1: power-domain@2 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg2: power-domain@3 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@4 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU_AHB>; > + }; > + > + pgc_gpu: power-domain@5 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > + power-domains = <&pgc_gpumix>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > -- > 2.20.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel