* [PATCH 0/2] Add critical interrupt and cooling maps for TSENS in SC7180
@ 2019-12-23 13:14 Rajeshwari
2019-12-23 13:14 ` [PATCH 1/2] arm64: dts: qcom: sc7180: " Rajeshwari
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
0 siblings, 2 replies; 9+ messages in thread
From: Rajeshwari @ 2019-12-23 13:14 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland, Bjorn Andersson,
Amit Kucheria, Zhang Rui, Daniel Lezcano
Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
manafm, Rajeshwari
Added critical interrupt support cooling maps support in SC7180 changed sensors
name under thermal-zones and added configuration for SC7180 in yaml.
Rajeshwari (2):
arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for
TSENS in SC7180.
dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml
.../devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 289 +++++++++++++++++----
2 files changed, 240 insertions(+), 50 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180.
2019-12-23 13:14 [PATCH 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
@ 2019-12-23 13:14 ` Rajeshwari
2019-12-27 6:22 ` Bjorn Andersson
2020-01-01 21:08 ` Amit Kucheria
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
1 sibling, 2 replies; 9+ messages in thread
From: Rajeshwari @ 2019-12-23 13:14 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland, Bjorn Andersson,
Amit Kucheria, Zhang Rui, Daniel Lezcano
Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
manafm, Rajeshwari
Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 289 +++++++++++++++++++++++++++++------
1 file changed, 239 insertions(+), 50 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3676bfd..e419ca0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -78,6 +79,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
@@ -94,6 +96,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
@@ -107,6 +110,7 @@
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
@@ -120,6 +124,7 @@
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
@@ -133,6 +138,7 @@
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
@@ -146,6 +152,7 @@
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
@@ -159,6 +166,7 @@
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
@@ -172,6 +180,7 @@
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
+ #cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
@@ -1058,8 +1067,9 @@
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
@@ -1068,8 +1078,9 @@
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <10>;
- interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
@@ -1301,277 +1312,455 @@
};
thermal-zones {
- cpu0-thermal {
+ cpu_0_0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
trips {
- cpu0_alert0: trip-point0 {
+ cpu_0_0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu0_alert1: trip-point1 {
+ cpu_0_0_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu0_crit: cpu_crit {
+ cpu_0_0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_0_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_0_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu1-thermal {
+ cpu_0_1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
trips {
- cpu1_alert0: trip-point0 {
+ cpu_0_1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu1_alert1: trip-point1 {
+ cpu_0_1_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu1_crit: cpu_crit {
+ cpu_0_1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_1_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_1_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu2-thermal {
+ cpu_0_2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
trips {
- cpu2_alert0: trip-point0 {
+ cpu_0_2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu2_alert1: trip-point1 {
+ cpu_0_2_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu2_crit: cpu_crit {
+ cpu_0_2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_2_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_2_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu3-thermal {
+ cpu_0_3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
trips {
- cpu3_alert0: trip-point0 {
+ cpu_0_3_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu3_alert1: trip-point1 {
+ cpu_0_3_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu3_crit: cpu_crit {
+ cpu_0_3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_3_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_3_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu4-thermal {
+ cpu_0_4-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
- cpu4_alert0: trip-point0 {
+ cpu_0_4_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu4_alert1: trip-point1 {
+ cpu_0_4_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu4_crit: cpu_crit {
+ cpu_0_4_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_4_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_4_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu5-thermal {
+ cpu_0_5-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
- cpu5_alert0: trip-point0 {
+ cpu_0_5_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu5_alert1: trip-point1 {
+ cpu_0_5_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu5_crit: cpu_crit {
+ cpu_0_5_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_0_5_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_0_5_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu6-thermal {
+ cpu_1_0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
trips {
- cpu6_alert0: trip-point0 {
+ cpu_1_0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu6_alert1: trip-point1 {
+ cpu_1_0_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu6_crit: cpu_crit {
+ cpu_1_0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_1_0_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_1_0_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu7-thermal {
+ cpu_1_1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
- cpu7_alert0: trip-point0 {
+ cpu_1_1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu7_alert1: trip-point1 {
+ cpu_1_1_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu7_crit: cpu_crit {
+ cpu_1_1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_1_1_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_1_1_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu8-thermal {
+ cpu_1_2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
trips {
- cpu8_alert0: trip-point0 {
+ cpu_1_2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu8_alert1: trip-point1 {
+ cpu_1_2_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu8_crit: cpu_crit {
+ cpu_1_2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_1_2_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_1_2_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- cpu9-thermal {
+ cpu_1_3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
trips {
- cpu9_alert0: trip-point0 {
+ cpu_1_3_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
- cpu9_alert1: trip-point1 {
+ cpu_1_3_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
- cpu9_crit: cpu_crit {
+ cpu_1_3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_1_3_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_1_3_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
- aoss0-thermal {
+ aoss_0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1586,7 +1775,7 @@
};
};
- cpuss0-thermal {
+ cpuss_0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1606,7 +1795,7 @@
};
};
- cpuss1-thermal {
+ cpuss_1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1626,7 +1815,7 @@
};
};
- gpuss0-thermal {
+ gpuss_0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1641,7 +1830,7 @@
};
};
- gpuss1-thermal {
+ gpuss_1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -1656,7 +1845,7 @@
};
};
- aoss1-thermal {
+ aoss_1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml
2019-12-23 13:14 [PATCH 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
2019-12-23 13:14 ` [PATCH 1/2] arm64: dts: qcom: sc7180: " Rajeshwari
@ 2019-12-23 13:14 ` Rajeshwari
2019-12-27 6:25 ` Bjorn Andersson
` (2 more replies)
1 sibling, 3 replies; 9+ messages in thread
From: Rajeshwari @ 2019-12-23 13:14 UTC (permalink / raw)
To: Andy Gross, Rob Herring, Mark Rutland, Bjorn Andersson,
Amit Kucheria, Zhang Rui, Daniel Lezcano
Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
manafm, Rajeshwari
Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
---
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index eef13b9..c0ed030 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -38,6 +38,7 @@ properties:
- enum:
- qcom,msm8996-tsens
- qcom,msm8998-tsens
+ - qcom,sc7180-tsens
- qcom,sdm845-tsens
- const: qcom,tsens-v2
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180.
2019-12-23 13:14 ` [PATCH 1/2] arm64: dts: qcom: sc7180: " Rajeshwari
@ 2019-12-27 6:22 ` Bjorn Andersson
2019-12-27 10:56 ` Rajeshwari Ravindra Kamble (Temp)
2020-01-01 21:08 ` Amit Kucheria
1 sibling, 1 reply; 9+ messages in thread
From: Bjorn Andersson @ 2019-12-27 6:22 UTC (permalink / raw)
To: Rajeshwari
Cc: Andy Gross, Rob Herring, Mark Rutland, Amit Kucheria, Zhang Rui,
Daniel Lezcano, linux-arm-msm, devicetree, linux-pm,
linux-kernel, sanm, sivaa, manafm
On Mon 23 Dec 05:14 PST 2019, Rajeshwari wrote:
This patch adds critical interrupt to tsens nodes, add cooling maps,
renames nodes and renames labels.
While the end result looks reasonable I would like to see this split in
a few different patches - and perhaps a line or two in the commit
message describing the new naming scheme for the renames.
Thanks,
Bjorn
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 289 +++++++++++++++++++++++++++++------
> 1 file changed, 239 insertions(+), 50 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 3676bfd..e419ca0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/phy/phy-qcom-qusb2.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -78,6 +79,7 @@
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_0: l2-cache {
> compatible = "cache";
> @@ -94,6 +96,7 @@
> reg = <0x0 0x100>;
> enable-method = "psci";
> next-level-cache = <&L2_100>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_100: l2-cache {
> compatible = "cache";
> @@ -107,6 +110,7 @@
> reg = <0x0 0x200>;
> enable-method = "psci";
> next-level-cache = <&L2_200>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_200: l2-cache {
> compatible = "cache";
> @@ -120,6 +124,7 @@
> reg = <0x0 0x300>;
> enable-method = "psci";
> next-level-cache = <&L2_300>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_300: l2-cache {
> compatible = "cache";
> @@ -133,6 +138,7 @@
> reg = <0x0 0x400>;
> enable-method = "psci";
> next-level-cache = <&L2_400>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_400: l2-cache {
> compatible = "cache";
> @@ -146,6 +152,7 @@
> reg = <0x0 0x500>;
> enable-method = "psci";
> next-level-cache = <&L2_500>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> L2_500: l2-cache {
> compatible = "cache";
> @@ -159,6 +166,7 @@
> reg = <0x0 0x600>;
> enable-method = "psci";
> next-level-cache = <&L2_600>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> L2_600: l2-cache {
> compatible = "cache";
> @@ -172,6 +180,7 @@
> reg = <0x0 0x700>;
> enable-method = "psci";
> next-level-cache = <&L2_700>;
> + #cooling-cells = <2>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> L2_700: l2-cache {
> compatible = "cache";
> @@ -1058,8 +1067,9 @@
> reg = <0 0x0c263000 0 0x1ff>, /* TM */
> <0 0x0c222000 0 0x1ff>; /* SROT */
> #qcom,sensors = <15>;
> - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "uplow";
> + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow","critical";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -1068,8 +1078,9 @@
> reg = <0 0x0c265000 0 0x1ff>, /* TM */
> <0 0x0c223000 0 0x1ff>; /* SROT */
> #qcom,sensors = <10>;
> - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "uplow";
> + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow","critical";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -1301,277 +1312,455 @@
> };
>
> thermal-zones {
> - cpu0-thermal {
> + cpu_0_0-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 1>;
>
> trips {
> - cpu0_alert0: trip-point0 {
> + cpu_0_0_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu0_alert1: trip-point1 {
> + cpu_0_0_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu0_crit: cpu_crit {
> + cpu_0_0_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_0_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_0_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu1-thermal {
> + cpu_0_1-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 2>;
>
> trips {
> - cpu1_alert0: trip-point0 {
> + cpu_0_1_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu1_alert1: trip-point1 {
> + cpu_0_1_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu1_crit: cpu_crit {
> + cpu_0_1_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_1_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_1_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu2-thermal {
> + cpu_0_2-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 3>;
>
> trips {
> - cpu2_alert0: trip-point0 {
> + cpu_0_2_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu2_alert1: trip-point1 {
> + cpu_0_2_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu2_crit: cpu_crit {
> + cpu_0_2_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_2_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_2_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu3-thermal {
> + cpu_0_3-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 4>;
>
> trips {
> - cpu3_alert0: trip-point0 {
> + cpu_0_3_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu3_alert1: trip-point1 {
> + cpu_0_3_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu3_crit: cpu_crit {
> + cpu_0_3_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_3_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_3_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu4-thermal {
> + cpu_0_4-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 5>;
>
> trips {
> - cpu4_alert0: trip-point0 {
> + cpu_0_4_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu4_alert1: trip-point1 {
> + cpu_0_4_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu4_crit: cpu_crit {
> + cpu_0_4_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_4_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_4_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu5-thermal {
> + cpu_0_5-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 6>;
>
> trips {
> - cpu5_alert0: trip-point0 {
> + cpu_0_5_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu5_alert1: trip-point1 {
> + cpu_0_5_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu5_crit: cpu_crit {
> + cpu_0_5_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_0_5_alert0>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_0_5_alert1>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu6-thermal {
> + cpu_1_0-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 9>;
>
> trips {
> - cpu6_alert0: trip-point0 {
> + cpu_1_0_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu6_alert1: trip-point1 {
> + cpu_1_0_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu6_crit: cpu_crit {
> + cpu_1_0_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_1_0_alert0>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_1_0_alert1>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu7-thermal {
> + cpu_1_1-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 10>;
>
> trips {
> - cpu7_alert0: trip-point0 {
> + cpu_1_1_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu7_alert1: trip-point1 {
> + cpu_1_1_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu7_crit: cpu_crit {
> + cpu_1_1_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_1_1_alert0>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_1_1_alert1>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu8-thermal {
> + cpu_1_2-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 11>;
>
> trips {
> - cpu8_alert0: trip-point0 {
> + cpu_1_2_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu8_alert1: trip-point1 {
> + cpu_1_2_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu8_crit: cpu_crit {
> + cpu_1_2_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_1_2_alert0>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_1_2_alert1>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - cpu9-thermal {
> + cpu_1_3-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 12>;
>
> trips {
> - cpu9_alert0: trip-point0 {
> + cpu_1_3_alert0: trip-point0 {
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu9_alert1: trip-point1 {
> + cpu_1_3_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu9_crit: cpu_crit {
> + cpu_1_3_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_1_3_alert0>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + map1 {
> + trip = <&cpu_1_3_alert1>;
> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> - aoss0-thermal {
> + aoss_0-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> @@ -1586,7 +1775,7 @@
> };
> };
>
> - cpuss0-thermal {
> + cpuss_0-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> @@ -1606,7 +1795,7 @@
> };
> };
>
> - cpuss1-thermal {
> + cpuss_1-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> @@ -1626,7 +1815,7 @@
> };
> };
>
> - gpuss0-thermal {
> + gpuss_0-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> @@ -1641,7 +1830,7 @@
> };
> };
>
> - gpuss1-thermal {
> + gpuss_1-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> @@ -1656,7 +1845,7 @@
> };
> };
>
> - aoss1-thermal {
> + aoss_1-thermal {
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
@ 2019-12-27 6:25 ` Bjorn Andersson
2020-01-01 21:09 ` Amit Kucheria
2020-01-08 16:25 ` Rob Herring
2 siblings, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2019-12-27 6:25 UTC (permalink / raw)
To: Rajeshwari
Cc: Andy Gross, Rob Herring, Mark Rutland, Amit Kucheria, Zhang Rui,
Daniel Lezcano, linux-arm-msm, devicetree, linux-pm,
linux-kernel, sanm, sivaa, manafm
On Mon 23 Dec 05:14 PST 2019, Rajeshwari wrote:
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index eef13b9..c0ed030 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -38,6 +38,7 @@ properties:
> - enum:
> - qcom,msm8996-tsens
> - qcom,msm8998-tsens
> + - qcom,sc7180-tsens
> - qcom,sdm845-tsens
> - const: qcom,tsens-v2
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180.
2019-12-27 6:22 ` Bjorn Andersson
@ 2019-12-27 10:56 ` Rajeshwari Ravindra Kamble (Temp)
0 siblings, 0 replies; 9+ messages in thread
From: Rajeshwari Ravindra Kamble (Temp) @ 2019-12-27 10:56 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, Amit Kucheria, Zhang Rui,
Daniel Lezcano, linux-arm-msm, devicetree, linux-pm,
linux-kernel, sanm, sivaa, manafm
On 12/27/2019 11:52 AM, Bjorn Andersson wrote:
> On Mon 23 Dec 05:14 PST 2019, Rajeshwari wrote:
>
> This patch adds critical interrupt to tsens nodes, add cooling maps,
> renames nodes and renames labels.
>
> While the end result looks reasonable I would like to see this split in
> a few different patches - and perhaps a line or two in the commit
> message describing the new naming scheme for the renames.
yeah sure, I'll provide separate patch for renames.
> Thanks,
> Rajeshwari
>
>> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7180.dtsi | 289 +++++++++++++++++++++++++++++------
>> 1 file changed, 239 insertions(+), 50 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 3676bfd..e419ca0 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -10,6 +10,7 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/phy/phy-qcom-qusb2.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/thermal/thermal.h>
>>
>> / {
>> interrupt-parent = <&intc>;
>> @@ -78,6 +79,7 @@
>> reg = <0x0 0x0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_0: l2-cache {
>> compatible = "cache";
>> @@ -94,6 +96,7 @@
>> reg = <0x0 0x100>;
>> enable-method = "psci";
>> next-level-cache = <&L2_100>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_100: l2-cache {
>> compatible = "cache";
>> @@ -107,6 +110,7 @@
>> reg = <0x0 0x200>;
>> enable-method = "psci";
>> next-level-cache = <&L2_200>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_200: l2-cache {
>> compatible = "cache";
>> @@ -120,6 +124,7 @@
>> reg = <0x0 0x300>;
>> enable-method = "psci";
>> next-level-cache = <&L2_300>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_300: l2-cache {
>> compatible = "cache";
>> @@ -133,6 +138,7 @@
>> reg = <0x0 0x400>;
>> enable-method = "psci";
>> next-level-cache = <&L2_400>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_400: l2-cache {
>> compatible = "cache";
>> @@ -146,6 +152,7 @@
>> reg = <0x0 0x500>;
>> enable-method = "psci";
>> next-level-cache = <&L2_500>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 0>;
>> L2_500: l2-cache {
>> compatible = "cache";
>> @@ -159,6 +166,7 @@
>> reg = <0x0 0x600>;
>> enable-method = "psci";
>> next-level-cache = <&L2_600>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 1>;
>> L2_600: l2-cache {
>> compatible = "cache";
>> @@ -172,6 +180,7 @@
>> reg = <0x0 0x700>;
>> enable-method = "psci";
>> next-level-cache = <&L2_700>;
>> + #cooling-cells = <2>;
>> qcom,freq-domain = <&cpufreq_hw 1>;
>> L2_700: l2-cache {
>> compatible = "cache";
>> @@ -1058,8 +1067,9 @@
>> reg = <0 0x0c263000 0 0x1ff>, /* TM */
>> <0 0x0c222000 0 0x1ff>; /* SROT */
>> #qcom,sensors = <15>;
>> - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
>> - interrupt-names = "uplow";
>> + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "uplow","critical";
>> #thermal-sensor-cells = <1>;
>> };
>>
>> @@ -1068,8 +1078,9 @@
>> reg = <0 0x0c265000 0 0x1ff>, /* TM */
>> <0 0x0c223000 0 0x1ff>; /* SROT */
>> #qcom,sensors = <10>;
>> - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
>> - interrupt-names = "uplow";
>> + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "uplow","critical";
>> #thermal-sensor-cells = <1>;
>> };
>>
>> @@ -1301,277 +1312,455 @@
>> };
>>
>> thermal-zones {
>> - cpu0-thermal {
>> + cpu_0_0-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 1>;
>>
>> trips {
>> - cpu0_alert0: trip-point0 {
>> + cpu_0_0_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu0_alert1: trip-point1 {
>> + cpu_0_0_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu0_crit: cpu_crit {
>> + cpu_0_0_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_0_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_0_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu1-thermal {
>> + cpu_0_1-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 2>;
>>
>> trips {
>> - cpu1_alert0: trip-point0 {
>> + cpu_0_1_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu1_alert1: trip-point1 {
>> + cpu_0_1_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu1_crit: cpu_crit {
>> + cpu_0_1_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_1_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_1_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu2-thermal {
>> + cpu_0_2-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 3>;
>>
>> trips {
>> - cpu2_alert0: trip-point0 {
>> + cpu_0_2_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu2_alert1: trip-point1 {
>> + cpu_0_2_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu2_crit: cpu_crit {
>> + cpu_0_2_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_2_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_2_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu3-thermal {
>> + cpu_0_3-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 4>;
>>
>> trips {
>> - cpu3_alert0: trip-point0 {
>> + cpu_0_3_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu3_alert1: trip-point1 {
>> + cpu_0_3_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu3_crit: cpu_crit {
>> + cpu_0_3_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_3_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_3_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu4-thermal {
>> + cpu_0_4-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 5>;
>>
>> trips {
>> - cpu4_alert0: trip-point0 {
>> + cpu_0_4_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu4_alert1: trip-point1 {
>> + cpu_0_4_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu4_crit: cpu_crit {
>> + cpu_0_4_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_4_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_4_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu5-thermal {
>> + cpu_0_5-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 6>;
>>
>> trips {
>> - cpu5_alert0: trip-point0 {
>> + cpu_0_5_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu5_alert1: trip-point1 {
>> + cpu_0_5_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu5_crit: cpu_crit {
>> + cpu_0_5_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_0_5_alert0>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_0_5_alert1>;
>> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu6-thermal {
>> + cpu_1_0-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 9>;
>>
>> trips {
>> - cpu6_alert0: trip-point0 {
>> + cpu_1_0_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu6_alert1: trip-point1 {
>> + cpu_1_0_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu6_crit: cpu_crit {
>> + cpu_1_0_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_1_0_alert0>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_1_0_alert1>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu7-thermal {
>> + cpu_1_1-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 10>;
>>
>> trips {
>> - cpu7_alert0: trip-point0 {
>> + cpu_1_1_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu7_alert1: trip-point1 {
>> + cpu_1_1_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu7_crit: cpu_crit {
>> + cpu_1_1_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_1_1_alert0>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_1_1_alert1>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu8-thermal {
>> + cpu_1_2-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 11>;
>>
>> trips {
>> - cpu8_alert0: trip-point0 {
>> + cpu_1_2_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu8_alert1: trip-point1 {
>> + cpu_1_2_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu8_crit: cpu_crit {
>> + cpu_1_2_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_1_2_alert0>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_1_2_alert1>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - cpu9-thermal {
>> + cpu_1_3-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> thermal-sensors = <&tsens0 12>;
>>
>> trips {
>> - cpu9_alert0: trip-point0 {
>> + cpu_1_3_alert0: trip-point0 {
>> temperature = <90000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu9_alert1: trip-point1 {
>> + cpu_1_3_alert1: trip-point1 {
>> temperature = <95000>;
>> hysteresis = <2000>;
>> type = "passive";
>> };
>>
>> - cpu9_crit: cpu_crit {
>> + cpu_1_3_crit: cpu_crit {
>> temperature = <110000>;
>> hysteresis = <1000>;
>> type = "critical";
>> };
>> };
>> +
>> + cooling-maps {
>> + map0 {
>> + trip = <&cpu_1_3_alert0>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + map1 {
>> + trip = <&cpu_1_3_alert1>;
>> + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> + };
>> + };
>> };
>>
>> - aoss0-thermal {
>> + aoss_0-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> @@ -1586,7 +1775,7 @@
>> };
>> };
>>
>> - cpuss0-thermal {
>> + cpuss_0-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> @@ -1606,7 +1795,7 @@
>> };
>> };
>>
>> - cpuss1-thermal {
>> + cpuss_1-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> @@ -1626,7 +1815,7 @@
>> };
>> };
>>
>> - gpuss0-thermal {
>> + gpuss_0-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> @@ -1641,7 +1830,7 @@
>> };
>> };
>>
>> - gpuss1-thermal {
>> + gpuss_1-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> @@ -1656,7 +1845,7 @@
>> };
>> };
>>
>> - aoss1-thermal {
>> + aoss_1-thermal {
>> polling-delay-passive = <250>;
>> polling-delay = <1000>;
>>
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180.
2019-12-23 13:14 ` [PATCH 1/2] arm64: dts: qcom: sc7180: " Rajeshwari
2019-12-27 6:22 ` Bjorn Andersson
@ 2020-01-01 21:08 ` Amit Kucheria
1 sibling, 0 replies; 9+ messages in thread
From: Amit Kucheria @ 2020-01-01 21:08 UTC (permalink / raw)
To: Rajeshwari
Cc: Andy Gross, Rob Herring, Mark Rutland, Bjorn Andersson,
Zhang Rui, Daniel Lezcano, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux PM list, LKML, sanm, sivaa, manafm
On Mon, Dec 23, 2019 at 6:46 PM Rajeshwari <rkambl@codeaurora.org> wrote:
>
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 289 +++++++++++++++++++++++++++++------
> 1 file changed, 239 insertions(+), 50 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 3676bfd..e419ca0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/phy/phy-qcom-qusb2.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/thermal/thermal.h>
<snip>
> - cpu1-thermal {
> + cpu_0_1-thermal {
Is this renaming to include the cluster number really improving
anything considering that the cpus section defines them as CPU0..CPU7?
Leave them as-is.
> polling-delay-passive = <250>;
> polling-delay = <1000>;
>
> thermal-sensors = <&tsens0 2>;
>
> trips {
> - cpu1_alert0: trip-point0 {
> + cpu_0_1_alert0: trip-point0 {
cpu_0_1_alert0 is unnecessarily too long, IMO. Leave it as-is. Same
for all the renames below.
> temperature = <90000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu1_alert1: trip-point1 {
> + cpu_0_1_alert1: trip-point1 {
> temperature = <95000>;
> hysteresis = <2000>;
> type = "passive";
> };
>
> - cpu1_crit: cpu_crit {
> + cpu_0_1_crit: cpu_crit {
> temperature = <110000>;
> hysteresis = <1000>;
> type = "critical";
> };
> };
<snip>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
2019-12-27 6:25 ` Bjorn Andersson
@ 2020-01-01 21:09 ` Amit Kucheria
2020-01-08 16:25 ` Rob Herring
2 siblings, 0 replies; 9+ messages in thread
From: Amit Kucheria @ 2020-01-01 21:09 UTC (permalink / raw)
To: Rajeshwari
Cc: Andy Gross, Rob Herring, Mark Rutland, Bjorn Andersson,
Zhang Rui, Daniel Lezcano, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux PM list, LKML, sanm, sivaa, manafm
On Mon, Dec 23, 2019 at 6:46 PM Rajeshwari <rkambl@codeaurora.org> wrote:
>
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index eef13b9..c0ed030 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -38,6 +38,7 @@ properties:
> - enum:
> - qcom,msm8996-tsens
> - qcom,msm8998-tsens
> + - qcom,sc7180-tsens
> - qcom,sdm845-tsens
> - const: qcom,tsens-v2
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
2019-12-27 6:25 ` Bjorn Andersson
2020-01-01 21:09 ` Amit Kucheria
@ 2020-01-08 16:25 ` Rob Herring
2 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2020-01-08 16:25 UTC (permalink / raw)
To: Rajeshwari
Cc: Andy Gross, Mark Rutland, Bjorn Andersson, Amit Kucheria,
Zhang Rui, Daniel Lezcano, linux-arm-msm, devicetree, linux-pm,
linux-kernel, sanm, sivaa, manafm, Rajeshwari
On Mon, 23 Dec 2019 18:44:31 +0530, Rajeshwari wrote:
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-01-08 16:25 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-23 13:14 [PATCH 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
2019-12-23 13:14 ` [PATCH 1/2] arm64: dts: qcom: sc7180: " Rajeshwari
2019-12-27 6:22 ` Bjorn Andersson
2019-12-27 10:56 ` Rajeshwari Ravindra Kamble (Temp)
2020-01-01 21:08 ` Amit Kucheria
2019-12-23 13:14 ` [PATCH 2/2] dt-bindings: thermal: tsens: Add configuration for sc7180 in yaml Rajeshwari
2019-12-27 6:25 ` Bjorn Andersson
2020-01-01 21:09 ` Amit Kucheria
2020-01-08 16:25 ` Rob Herring
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