From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43F57C4727C for ; Thu, 1 Oct 2020 08:59:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC07220BED for ; Thu, 1 Oct 2020 08:59:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601542783; bh=dxjby0k4ruLwHuefwwJvXuvzJQNaPvKX3XCpTvZTRCM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=S/xTYMMfvApZGXIW+7aJQt3ZM+GiEHedGG6qczca9cUayT4jUej3ox7cIucvyDj3R Bev/ar3TlQmhK+NxQ5+eqs6lKVFhk65qyZauzgTPcWvTWEm4or1MKBTnH0OYZUz7Ri HdVgkF+cuU1u5b19Dnhdi9uU6KGL6dtq63Nl+KOg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725975AbgJAI7m (ORCPT ); Thu, 1 Oct 2020 04:59:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:43612 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725894AbgJAI7m (ORCPT ); Thu, 1 Oct 2020 04:59:42 -0400 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 913E320BED for ; Thu, 1 Oct 2020 08:59:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601542781; bh=dxjby0k4ruLwHuefwwJvXuvzJQNaPvKX3XCpTvZTRCM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Kx4RWEsmwMlKo2SzSFITiZFfDMjwJcFrkAWQlVpKSnDSWi6udeSq8QCGHrZs/sYo5 6oucwe9d7kRUToShABZ1ivYwv70Fvhm6bjhemhTbqPu4Sc2ghVP/xM8JNcc0qFETQJ LAXsdQhVfIO4I+z4HtxOA1F0WtMHMEU34JyvCkac= Received: by mail-ed1-f53.google.com with SMTP id b12so4778536edz.11 for ; Thu, 01 Oct 2020 01:59:41 -0700 (PDT) X-Gm-Message-State: AOAM530RwHN2B44gv7NAhbwlMHmq43cIuKaSdqvyg8Jf6XL2lRwmNZJZ RmgIyXkuOUKx9Y3k5rvVWHdgrK0a0AYcct3QrLQ= X-Google-Smtp-Source: ABdhPJwUjk9wE19HiYa3JYp+FUpf9iC9/3rDAVR8kbLcgeAE1A3Y/+vLDwP6i33Po/TVw9jWZyfHlUOvWS4rhI7kkPQ= X-Received: by 2002:a50:e78f:: with SMTP id b15mr7208895edn.104.1601542780136; Thu, 01 Oct 2020 01:59:40 -0700 (PDT) MIME-Version: 1.0 References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-8-l.stach@pengutronix.de> In-Reply-To: <20200930155006.535712-8-l.stach@pengutronix.de> From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 10:59:27 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 07/11] soc: imx: gpcv2: add support for optional resets To: Lucas Stach Cc: Shawn Guo , Rob Herring , NXP Linux Team , Fabio Estevam , Frieder Schrempf , Marek Vasut , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 30 Sep 2020 at 17:52, Lucas Stach wrote: > > Normally the reset for the devices inside the power domain is > triggered automatically from the PGC in the power-up sequencing, > however on i.MX8MM this doesn't work for the GPU power domains. > > Add support for triggering the reset explicitly during the power > up sequencing. > > Signed-off-by: Lucas Stach > --- > .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 6 ++++++ > drivers/soc/imx/gpcv2.c | 13 +++++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > index bde09a0b2da3..9773771b9000 100644 > --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > @@ -62,6 +62,12 @@ properties: > > power-supply: true > > + resets: > + description: | > + A number of phandles to resets that need to be asserted during > + power-up sequencing of the domain. > + minItems: 1 > + > required: > - '#power-domain-cells' > - reg Separate patch for dt-bindings, please. Best regards, Krzysztof