From: Chuanhong Guo <gch981213@gmail.com>
To: Oleksij Rempel <linux@rempel-privat.de>
Cc: "open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
Rob Herring <robh@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, Stephen Boyd <sboyd@kernel.org>,
James Hogan <jhogan@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
Ralf Baechle <ralf@linux-mips.org>,
open list <linux-kernel@vger.kernel.org>,
Paul Burton <paul.burton@mips.com>,
Weijie Gao <hackpascal@gmail.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
John Crispin <john@phrozen.org>, NeilBrown <neil@brown.name>,
Mark Rutland <mark.rutland@arm.com>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation
Date: Sun, 18 Aug 2019 10:29:29 +0800 [thread overview]
Message-ID: <CAJsYDVLLPa07wUg2EoeJww9XSJYgX_kBu-oGiv7n+zejUc877w@mail.gmail.com> (raw)
In-Reply-To: <6b6ee744-61d3-8848-19e7-0a301fe4d1b3@rempel-privat.de>
Hi!
On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel <linux@rempel-privat.de> wrote:
> >> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks.
> >> Jist wild assumption. All peripheral devices are suing bus clock.
> >
> > This assumption is incorrect. When this patchset is applied in
> > OpenWrt, I asked the author why there's still a fixed clock in
> > mt7621.dtsi, He told me that there's another clock for those unchanged
> > peripherals and he doesn't have time to write a clock provider for it.
>
> Can you please provide a link to this patch or email.
This discussion is in Chinese and using an IM software so there's no
link available.
> We have at least 2 know registers:
> SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped
> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
> SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
> all or some ip cores.
> What is probably missing is a set of dividers for
> each ip core. From your words it is not document.
The specific missing part I was referring to, is parent clocks for
every gates. I'm not going to assume this with current openwrt device
tree because some peripherals doesn't have a clock binding at all or
have a dummy one there.
>
> With this information the clk driver will provide gate functionality and
> a set of hardcoded clocks. With this driver will work part of power
> management and nice devicetree without fixed clocks.
Regards,
Chuanhong Guo
next prev parent reply other threads:[~2019-08-18 2:29 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-24 2:23 [PATCH v2 0/6] MIPS: ralink: add CPU clock detection for MT7621 Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 1/6] dt-bindings: clock: add dt binding header for mt7621-pll Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 2/6] MIPS: ralink: drop ralink_clk_init for mt7621 Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 3/6] MIPS: ralink: add clock device providing cpu/bus clock " Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation Chuanhong Guo
2019-07-29 17:33 ` Paul Burton
2019-08-13 15:51 ` Rob Herring
2019-08-17 14:42 ` Chuanhong Guo
2019-08-17 15:39 ` Oleksij Rempel
2019-08-17 16:22 ` Chuanhong Guo
2019-08-17 18:05 ` Oleksij Rempel
2019-08-18 2:29 ` Chuanhong Guo [this message]
2019-08-18 6:10 ` Oleksij Rempel
2019-08-18 7:19 ` Chuanhong Guo
2019-08-18 7:59 ` Oleksij Rempel
2019-08-18 8:26 ` Chuanhong Guo
2019-08-18 8:44 ` Chuanhong Guo
2019-08-18 9:51 ` Oleksij Rempel
2019-08-18 10:07 ` Chuanhong Guo
2019-08-17 15:40 ` Oleksij Rempel
2019-07-24 2:23 ` [PATCH v2 5/6] staging: mt7621-dts: fix register range of memc node in mt7621.dtsi Chuanhong Guo
2019-07-24 2:23 ` [PATCH v2 6/6] staging: mt7621-dts: add dt nodes for mt7621-pll Chuanhong Guo
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