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From: Shubhrajyoti Datta <shubhrajyoti.datta-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Jolly Shah <jolly.shah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Cc: ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
	mingo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	Greg Kroah-Hartman
	<gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>,
	matt-mF/unelCI9GS6iBeEJttW/XRex20P6io@public.gmane.org,
	sudeep.holla-5wv7dgnIgG8@public.gmane.org,
	hkallweit1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	keescook-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	dmitry.torokhov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	Michal Simek
	<michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Jolly Shah <jollys-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
	Rajan Vaja <rajanv-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP firmware driver
Date: Tue, 30 Jan 2018 10:35:52 +0530	[thread overview]
Message-ID: <CAKfKVtGGf8AexOTEvyyi7cmQ_Xopa3Fszf-jOuNSfBJpE2EzCg@mail.gmail.com> (raw)
In-Reply-To: <1516836074-4149-3-git-send-email-jollys-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>

Hi,

Thanks for the patch.
A few questions below.


On Thu, Jan 25, 2018 at 4:51 AM, Jolly Shah <jolly.shah-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
> This patch is adding communication layer with firmware.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate to
> PMUFW(Platform Management Unit). All requests go through ATF.
>
> Signed-off-by: Jolly Shah <jollys-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Rajan Vaja <rajanv-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> ---
<snip>
>

> +/**
> + * zynqmp_pm_clock_enable - Enable the clock for given id
> + * @clock_id:  ID of the clock to be enabled

Does it enable all the parents also if they are disabled?

> + *
> + * This function is used by master to enable the clock
> + * including peripherals and PLL clocks.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
> +static int zynqmp_pm_clock_enable(u32 clock_id)
> +{
> +       return invoke_pm_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL);
> +}
> +
> +/**
> + * zynqmp_pm_clock_disable - Disable the clock for given id
> + * @clock_id:  ID of the clock to be disable
> + *
> + * This function is used by master to disable the clock
> + * including peripherals and PLL clocks.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
> +static int zynqmp_pm_clock_disable(u32 clock_id)
> +{
> +       return invoke_pm_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL);
> +}
> +
> +/**
> + * zynqmp_pm_clock_getstate - Get the clock state for given id
> + * @clock_id:  ID of the clock to be queried
> + * @state:     1/0 (Enabled/Disabled)
> + *
> + * This function is used by master to get the state of clock
> + * including peripherals and PLL clocks.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
> +static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
> +{
> +       u32 ret_payload[PAYLOAD_ARG_CNT];
> +       int ret;
> +
> +       ret = invoke_pm_fn(PM_CLOCK_GETSTATE, clock_id, 0, 0, 0, ret_payload);
> +       *state = ret_payload[1];
> +
> +       return ret;
> +}
> +
> +/**
> + * zynqmp_pm_clock_setdivider - Set the clock divider for given id
> + * @clock_id:  ID of the clock
> + * @div_type:  TYPE_DIV1: div1
> + *             TYPE_DIV2: div2
div type didnt see in the signature.



> + * @divider:   divider value.
> + *
> + * This function is used by master to set divider for any clock
> + * to achieve desired rate.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
> +static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
> +{
> +       return invoke_pm_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL);
> +}
> +
> +/**
> + * zynqmp_pm_clock_getdivider - Get the clock divider for given id
> + * @clock_id:  ID of the clock
> + * @div_type:  TYPE_DIV1: div1
> + *             TYPE_DIV2: div2
didnt see this  below.

> + * @divider:   divider value.
> + *
> + * This function is used by master to get divider values
> + * for any clock.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
> +static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
> +{
> +       u32 ret_payload[PAYLOAD_ARG_CNT];
> +       int ret;
> +
> +       ret = invoke_pm_fn(PM_CLOCK_GETDIVIDER, clock_id, 0, 0, 0, ret_payload);
> +       *divider = ret_payload[1];
> +
> +       return ret;
> +}
> +
> +/**
> + * zynqmp_pm_clock_setrate - Set the clock rate for given id
> + * @clock_id:  ID of the clock
> + * @rate:      rate value in hz
> + *
> + * This function is used by master to set rate for any clock.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
So this can set rate only 4G max ?

> +static int zynqmp_pm_clock_setrate(u32 clock_id, u32 rate)
> +{
> +       return invoke_pm_fn(PM_CLOCK_SETRATE, clock_id, rate, 0, 0, NULL);
> +}
> +
> +/**
> + * zynqmp_pm_clock_getrate - Get the clock rate for given id
> + * @clock_id:  ID of the clock
> + * @rate:      rate value in hz
> + *
> + * This function is used by master to get rate
> + * for any clock.
> + *
> + * Return:     Returns status, either success or error+reason.
> + */
Same question here?

> +static int zynqmp_pm_clock_getrate(u32 clock_id, u32 *rate)
> +{
> +       u32 ret_payload[PAYLOAD_ARG_CNT];
> +       int ret;
> +
> +       ret = invoke_pm_fn(PM_CLOCK_GETRATE, clock_id, 0, 0, 0, ret_payload);
> +       *rate = ret_payload[1];
> +
> +       return ret;
> +}
> +
Also  what is the difference between set rate and set divider?
--
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  parent reply	other threads:[~2018-01-30  5:05 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-24 23:21 [PATCH v3 0/4] drivers: firmware: xilinx: Add firmware driver support Jolly Shah
     [not found] ` <1516836074-4149-1-git-send-email-jollys-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2018-01-24 23:21   ` [PATCH v3 1/4] dt-bindings: firmware: Add bindings for ZynqMP firmware Jolly Shah
2018-01-30 17:08     ` Rob Herring
2018-01-31 18:03       ` Jolly Shah
2018-02-01 15:11         ` Rob Herring
2018-01-31 18:03     ` Mark Rutland
     [not found]       ` <20180131180354.mqf4gvvprdtycbn5-agMKViyK24J5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org>
2018-02-01  1:04         ` Jolly Shah
     [not found]           ` <CY1PR0201MB076454E915A6E6947A39F04BB8FA0-w5HSbVcoX6AJQdFqRSmStRrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-02-01 10:27             ` Mark Rutland
2018-02-02 19:50               ` Jolly Shah
2018-01-24 23:21 ` [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP firmware driver Jolly Shah
     [not found]   ` <1516836074-4149-3-git-send-email-jollys-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2018-01-30  5:05     ` Shubhrajyoti Datta [this message]
2018-01-31 19:46       ` Jolly Shah
2018-01-31 18:20     ` Mark Rutland
     [not found]       ` <20180131182012.oshjmvahetaizlbu-agMKViyK24J5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org>
2018-02-01  1:23         ` Jolly Shah
     [not found]           ` <CY1PR0201MB0764D88D409A35B8379323B4B8FA0-w5HSbVcoX6AJQdFqRSmStRrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-02-01 10:33             ` Mark Rutland
     [not found]               ` <20180201103321.fftn37mgzbk6oltl-agMKViyK24J5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org>
2018-02-01 23:54                 ` Jolly Shah
2018-01-24 23:21 ` [PATCH v3 3/4] drivers: firmware: xilinx: Add sysfs interface Jolly Shah
2018-01-24 23:21 ` [PATCH v3 4/4] drivers: firmware: xilinx: Add debugfs interface Jolly Shah
2018-01-25  9:30   ` Greg KH
     [not found]     ` <20180125093057.GA1936-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
2018-01-31 19:48       ` Jolly Shah

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