[PATCH 1/3] dt-bindings: PCI: Convert Arm Versatile binding to DT schema

[PATCH 1/3] dt-bindings: PCI: Convert Arm Versatile binding to DT schema

[Rob Herring]

Convert the Arm Versatile PCI host binding to a DT schema.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/versatile.txt     | 59 ------------
 .../devicetree/bindings/pci/versatile.yaml    | 92 +++++++++++++++++++
 MAINTAINERS                                   |  2 +-
 3 files changed, 93 insertions(+), 60 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/versatile.txt
 create mode 100644 Documentation/devicetree/bindings/pci/versatile.yaml

diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt
deleted file mode 100644
index 0a702b13d2ac..000000000000
--- a/Documentation/devicetree/bindings/pci/versatile.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* ARM Versatile Platform Baseboard PCI interface
-
-PCI host controller found on the ARM Versatile PB board's FPGA.
-
-Required properties:
-- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
-  controller.
-- reg: base addresses and lengths of the PCI controller. There must be 3
-  entries:
-	- Versatile-specific registers
-	- Self Config space
-	- Config space
-- #address-cells: set to <3>
-- #size-cells: set to <2>
-- device_type: set to "pci"
-- bus-range: set to <0 0xff>
-- ranges: ranges for the PCI memory and I/O regions
-- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties to define
-	the mapping of the PCI interface to interrupt numbers.
-
-Example:
-
-pci-controller@10001000 {
-	compatible = "arm,versatile-pci";
-	device_type = "pci";
-	reg = <0x10001000 0x1000
-	       0x41000000 0x10000
-	       0x42000000 0x100000>;
-	bus-range = <0 0xff>;
-	#address-cells = <3>;
-	#size-cells = <2>;
-	#interrupt-cells = <1>;
-
-	ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */
-		  0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */
-		  0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
-
-	interrupt-map-mask = <0x1800 0 0 7>;
-	interrupt-map = <0x1800 0 0 1 &sic 28
-			 0x1800 0 0 2 &sic 29
-			 0x1800 0 0 3 &sic 30
-			 0x1800 0 0 4 &sic 27
-
-			 0x1000 0 0 1 &sic 27
-			 0x1000 0 0 2 &sic 28
-			 0x1000 0 0 3 &sic 29
-			 0x1000 0 0 4 &sic 30
-
-			 0x0800 0 0 1 &sic 30
-			 0x0800 0 0 2 &sic 27
-			 0x0800 0 0 3 &sic 28
-			 0x0800 0 0 4 &sic 29
-
-			 0x0000 0 0 1 &sic 29
-			 0x0000 0 0 2 &sic 30
-			 0x0000 0 0 3 &sic 27
-			 0x0000 0 0 4 &sic 28>;
-};
diff --git a/Documentation/devicetree/bindings/pci/versatile.yaml b/Documentation/devicetree/bindings/pci/versatile.yaml
new file mode 100644
index 000000000000..07a48c27db1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/versatile.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/versatile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Versatile Platform Baseboard PCI interface
+
+maintainers:
+  - Rob Herring <robh@kernel.org>
+
+description: |+
+  PCI host controller found on the ARM Versatile PB board's FPGA.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: arm,versatile-pci
+
+  reg:
+    items:
+      - description: Versatile-specific registers
+      - description: Self Config space
+      - description: Config space
+
+  ranges:
+    maxItems: 3
+
+  "#interrupt-cells": true
+
+  interrupt-map:
+    maxItems: 16
+
+  interrupt-map-mask:
+    items:
+      - const: 0x1800
+      - const: 0
+      - const: 0
+      - const: 7
+
+required:
+  - compatible
+  - reg
+  - ranges
+  - "#interrupt-cells"
+  - interrupt-map
+  - interrupt-map-mask
+
+examples:
+  - |
+    pci@10001000 {
+      compatible = "arm,versatile-pci";
+      device_type = "pci";
+      reg = <0x10001000 0x1000>,
+            <0x41000000 0x10000>,
+            <0x42000000 0x100000>;
+      bus-range = <0 0xff>;
+      #address-cells = <3>;
+      #size-cells = <2>;
+      #interrupt-cells = <1>;
+
+      ranges =
+          <0x01000000 0 0x00000000 0x43000000 0 0x00010000>,  /* downstream I/O */
+          <0x02000000 0 0x50000000 0x50000000 0 0x10000000>,  /* non-prefetchable memory */
+          <0x42000000 0 0x60000000 0x60000000 0 0x10000000>;  /* prefetchable memory */
+
+      interrupt-map-mask = <0x1800 0 0 7>;
+      interrupt-map = <0x1800 0 0 1 &sic 28>,
+          <0x1800 0 0 2 &sic 29>,
+          <0x1800 0 0 3 &sic 30>,
+          <0x1800 0 0 4 &sic 27>,
+
+          <0x1000 0 0 1 &sic 27>,
+          <0x1000 0 0 2 &sic 28>,
+          <0x1000 0 0 3 &sic 29>,
+          <0x1000 0 0 4 &sic 30>,
+
+          <0x0800 0 0 1 &sic 30>,
+          <0x0800 0 0 2 &sic 27>,
+          <0x0800 0 0 3 &sic 28>,
+          <0x0800 0 0 4 &sic 29>,
+
+          <0x0000 0 0 1 &sic 29>,
+          <0x0000 0 0 2 &sic 30>,
+          <0x0000 0 0 3 &sic 27>,
+          <0x0000 0 0 4 &sic 28>;
+    };
+
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index c6c34d04ce95..48a90f0833b8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12401,7 +12401,7 @@ M:	Rob Herring <robh@kernel.org>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/versatile.txt
+F:	Documentation/devicetree/bindings/pci/versatile.yaml
 F:	drivers/pci/controller/pci-versatile.c
 
 PCI DRIVER FOR ARMADA 8K
-- 
2.20.1

[PATCH 2/3] dt-bindings: PCI: Convert Cadence host to DT schema

[Rob Herring]

Convert the Cadence PCIe host binding to DT schema.

The 'phy-names' definition is incomplete.

'vendor-id' and 'device-id' aren't listed as those are standard PCI
properties. They were incorrectly defined as 16-bit when they should be
32-bits (even though only 16-bits are used).

'cdns,max-outbound-regions' should really be removed. It serves no
purpose other than bounds checking 'ranges'. If 'ranges' is wrong for
the h/w, what's going to ensure 'cdns,max-outbound-regions' is correct.

'cdns,no-bar-match-nbits' is also suspect. This probably could be
determined from 'dma-ranges' using the sizes.

Cc: Alan Douglas <adouglas@cadence.com>
Cc: Scott Telford <stelford@cadence.com>
Cc: Tom Joseph <tjoseph@cadence.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 .../bindings/pci/cdns,cdns-pcie-host.txt      |  66 -----------
 .../bindings/pci/cdns,cdns-pcie-host.yaml     | 106 ++++++++++++++++++
 MAINTAINERS                                   |   2 +-
 3 files changed, 107 insertions(+), 67 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
 create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
deleted file mode 100644
index 91de69c713a9..000000000000
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-* Cadence PCIe host controller
-
-This PCIe controller inherits the base properties defined in
-host-generic-pci.txt.
-
-Required properties:
-- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
-- reg: Should contain the controller register base address, PCIe configuration
-  window base address, and AXI interface region base address respectively.
-- reg-names: Must be "reg", "cfg" and "mem" respectively.
-- #address-cells: Set to <3>
-- #size-cells: Set to <2>
-- device_type: Set to "pci"
-- ranges: Ranges for the PCI memory and I/O regions
-- #interrupt-cells: Set to <1>
-- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
-  mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- cdns,max-outbound-regions: Set to maximum number of outbound regions
-  (default 32)
-- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
-  number of least significant bits kept during inbound (PCIe -> AXI) address
-  translations (default 32)
-- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
-- device-id: The PCI device ID (16 bits, default is design dependent)
-- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
-  than one in the list.  If only one PHY listed it must manage all lanes. 
-- phy-names:  List of names to identify the PHY.
-
-Example:
-
-pcie@fb000000 {
-	compatible = "cdns,cdns-pcie-host";
-	device_type = "pci";
-	#address-cells = <3>;
-	#size-cells = <2>;
-	bus-range = <0x0 0xff>;
-	linux,pci-domain = <0>;
-	cdns,max-outbound-regions = <16>;
-	cdns,no-bar-match-nbits = <32>;
-	vendor-id = /bits/ 16 <0x17cd>;
-	device-id = /bits/ 16 <0x0200>;
-
-	reg = <0x0 0xfb000000  0x0 0x01000000>,
-	      <0x0 0x41000000  0x0 0x00001000>,
-	      <0x0 0x40000000  0x0 0x04000000>;
-	reg-names = "reg", "cfg", "mem";
-
-	ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
-		 <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
-
-	#interrupt-cells = <0x1>;
-
-	interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1
-			 0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1
-			 0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1
-			 0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;
-
-	interrupt-map-mask = <0x0 0x0 0x0  0x7>;
-
-	msi-parent = <&its_pci>;
-
-	phys = <&pcie_phy0>;
-	phy-names = "pcie-phy";
-};
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
new file mode 100644
index 000000000000..ada77e267b68
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence PCIe host controller
+
+maintainers:
+  - Alan Douglas <adouglas@cadence.com>
+  - Scott Telford <stelford@cadence.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    const: cdns,cdns-pcie-host
+
+  reg:
+    maxItems: 3
+
+  reg-names:
+    items:
+      - const: reg
+      - const: cfg
+      - const: mem
+
+  cdns,max-outbound-regions:
+    description: maximum number of outbound regions
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 32
+    default: 32
+
+  cdns,no-bar-match-nbits:
+    description:
+      Set into the no BAR match register to configure the number of least
+      significant bits kept during inbound (PCIe -> AXI) address translations
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 32
+    default: 32
+
+  msi-parent: true
+
+  phys:
+    description:
+      One per lane if more than one in the list. If only one PHY listed it must
+      manage all lanes.
+    minItems: 1
+    maxItems: 16
+
+  phy-names:
+    items:
+      - const: pcie-phy
+    # FIXME: names when more than 1
+
+required:
+  - reg
+  - reg-names
+
+examples:
+  - |
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie@fb000000 {
+            compatible = "cdns,cdns-pcie-host";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            bus-range = <0x0 0xff>;
+            linux,pci-domain = <0>;
+            cdns,max-outbound-regions = <16>;
+            cdns,no-bar-match-nbits = <32>;
+            vendor-id = /bits/ 16 <0x17cd>;
+            device-id = /bits/ 16 <0x0200>;
+
+            reg = <0x0 0xfb000000  0x0 0x01000000>,
+                  <0x0 0x41000000  0x0 0x00001000>,
+                  <0x0 0x40000000  0x0 0x04000000>;
+            reg-names = "reg", "cfg", "mem";
+
+            ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
+                     <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
+
+            #interrupt-cells = <0x1>;
+
+            interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1>,
+                 <0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1>,
+                 <0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1>,
+                 <0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;
+
+            interrupt-map-mask = <0x0 0x0 0x0  0x7>;
+
+            msi-parent = <&its_pci>;
+
+            phys = <&pcie_phy0>;
+            phy-names = "pcie-phy";
+        };
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 48a90f0833b8..21f3393c36e3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12416,7 +12416,7 @@ PCI DRIVER FOR CADENCE PCIE IP
 M:	Tom Joseph <tjoseph@cadence.com>
 L:	linux-pci@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/cdns,*.txt
+F:	Documentation/devicetree/bindings/pci/cdns,*
 F:	drivers/pci/controller/pcie-cadence*
 
 PCI DRIVER FOR FREESCALE LAYERSCAPE
-- 
2.20.1

[PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Rob Herring]

Convert the generic PCI host binding to DT schema. The derivative Juno,
PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
their compatible strings. The simplest way to convert those to
schema is just add them into the common generic PCI host schema.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Andrew Murray <andrew.murray@arm.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Will Deacon <will@kernel.org>
Cc: David Daney <david.daney@cavium.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 .../bindings/pci/arm,juno-r1-pcie.txt         |  10 --
 .../bindings/pci/designware-pcie-ecam.txt     |  42 -----
 .../bindings/pci/hisilicon-pcie.txt           |   4 +-
 .../bindings/pci/host-generic-pci.txt         | 101 ------------
 .../bindings/pci/host-generic-pci.yaml        | 150 ++++++++++++++++++
 .../bindings/pci/pci-thunder-ecam.txt         |  30 ----
 .../bindings/pci/pci-thunder-pem.txt          |   7 +-
 .../bindings/pci/plda,xpressrich3-axi.txt     |  12 --
 MAINTAINERS                                   |   2 +-
 9 files changed, 155 insertions(+), 203 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt
 create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt

diff --git a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt b/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
deleted file mode 100644
index f7514c170a32..000000000000
--- a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-* ARM Juno R1 PCIe interface
-
-This PCIe host controller is based on PLDA XpressRICH3-AXI IP
-and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
-as well as the base properties defined in host-generic-pci.txt.
-
-Required properties:
- - compatible: "arm,juno-r1-pcie"
- - dma-coherent: The host controller bridges the AXI transactions into PCIe bus
-   in a manner that makes the DMA operations to appear coherent to the CPUs.
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
deleted file mode 100644
index 515b2f9542e5..000000000000
--- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Synopsys DesignWare PCIe root complex in ECAM shift mode
-
-In some cases, firmware may already have configured the Synopsys DesignWare
-PCIe controller in RC mode with static ATU window mappings that cover all
-config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion.
-In this case, there is no need for the OS to perform any low level setup
-of clocks, PHYs or device registers, nor is there any reason for the driver
-to reconfigure ATU windows for config and/or IO space accesses at runtime.
-
-In cases where the IP was synthesized with a minimum ATU window size of
-64 KB, it cannot be supported by the generic ECAM driver, because it
-requires special config space accessors that filter accesses to device #1
-and beyond on the first bus.
-
-Required properties:
-- compatible: "marvell,armada8k-pcie-ecam" or
-              "socionext,synquacer-pcie-ecam" or
-              "snps,dw-pcie-ecam" (must be preceded by a more specific match)
-
-Please refer to the binding document of "pci-host-ecam-generic" in the
-file host-generic-pci.txt for a description of the remaining required
-and optional properties.
-
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
-        interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;
-        msi-map = <0x0 &its 0x0 0x10000>;
-        dma-coherent;
-    };
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 0dcb87d6554f..adf66a26b70b 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -49,10 +49,10 @@ compliant for all devices other than the root complex. In such cases,
 the host controller should be described as below.
 
 The properties and their meanings are identical to those described in
-host-generic-pci.txt except as listed below.
+host-generic-pci.yaml except as listed below.
 
 Properties of the host controller node that differ from
-host-generic-pci.txt:
+host-generic-pci.yaml:
 
 - compatible     : Must be "hisilicon,hip06-pcie-ecam", or
 		   "hisilicon,hip07-pcie-ecam"
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
deleted file mode 100644
index 614b594f4e72..000000000000
--- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
+++ /dev/null
@@ -1,101 +0,0 @@
-* Generic PCI host controller
-
-Firmware-initialised PCI host controllers and PCI emulations, such as the
-virtio-pci implementations found in kvmtool and other para-virtualised
-systems, do not require driver support for complexities such as regulator
-and clock management. In fact, the controller may not even require the
-configuration of a control interface by the operating system, instead
-presenting a set of fixed windows describing a subset of IO, Memory and
-Configuration Spaces.
-
-Such a controller can be described purely in terms of the standardized device
-tree bindings communicated in pci.txt:
-
-
-Properties of the host controller node:
-
-- compatible     : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
-                   depending on the layout of configuration space (CAM vs
-                   ECAM respectively).
-
-- device_type    : Must be "pci".
-
-- ranges         : As described in IEEE Std 1275-1994, but must provide
-                   at least a definition of non-prefetchable memory. One
-                   or both of prefetchable Memory and IO Space may also
-                   be provided.
-
-- bus-range      : Optional property (also described in IEEE Std 1275-1994)
-                   to indicate the range of bus numbers for this controller.
-                   If absent, defaults to <0 255> (i.e. all buses).
-
-- #address-cells : Must be 3.
-
-- #size-cells    : Must be 2.
-
-- reg            : The Configuration Space base address and size, as accessed
-                   from the parent bus.  The base address corresponds to
-                   the first bus in the "bus-range" property.  If no
-                   "bus-range" is specified, this will be bus 0 (the default).
-
-Properties of the /chosen node:
-
-- linux,pci-probe-only
-                 : Optional property which takes a single-cell argument.
-                   If '0', then Linux will assign devices in its usual manner,
-                   otherwise it will not try to assign devices and instead use
-                   them as they are configured already.
-
-Configuration Space is assumed to be memory-mapped (as opposed to being
-accessed via an ioport) and laid out with a direct correspondence to the
-geography of a PCI bus address by concatenating the various components to
-form an offset.
-
-For CAM, this 24-bit offset is:
-
-        cfg_offset(bus, device, function, register) =
-                   bus << 16 | device << 11 | function << 8 | register
-
-While ECAM extends this by 4 bits to accommodate 4k of function space:
-
-        cfg_offset(bus, device, function, register) =
-                   bus << 20 | device << 15 | function << 12 | register
-
-Interrupt mapping is exactly as described in `Open Firmware Recommended
-Practice: Interrupt Mapping' and requires the following properties:
-
-- #interrupt-cells   : Must be 1
-
-- interrupt-map      : <see aforementioned specification>
-
-- interrupt-map-mask : <see aforementioned specification>
-
-
-Example:
-
-pci {
-    compatible = "pci-host-cam-generic"
-    device_type = "pci";
-    #address-cells = <3>;
-    #size-cells = <2>;
-    bus-range = <0x0 0x1>;
-
-    // CPU_PHYSICAL(2)  SIZE(2)
-    reg = <0x0 0x40000000  0x0 0x1000000>;
-
-    // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
-    ranges = <0x01000000 0x0 0x01000000  0x0 0x01000000  0x0 0x00010000>,
-             <0x02000000 0x0 0x41000000  0x0 0x41000000  0x0 0x3f000000>;
-
-
-    #interrupt-cells = <0x1>;
-
-    // PCI_DEVICE(3)  INT#(1)  CONTROLLER(PHANDLE)  CONTROLLER_DATA(3)
-    interrupt-map = <  0x0 0x0 0x0  0x1  &gic  0x0 0x4 0x1
-                     0x800 0x0 0x0  0x1  &gic  0x0 0x5 0x1
-                    0x1000 0x0 0x0  0x1  &gic  0x0 0x6 0x1
-                    0x1800 0x0 0x0  0x1  &gic  0x0 0x7 0x1>;
-
-    // PCI_DEVICE(3)  INT#(1)
-    interrupt-map-mask = <0xf800 0x0 0x0  0x7>;
-}
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
new file mode 100644
index 000000000000..7c3f3b2bdd57
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic PCI host controller
+
+maintainers:
+  - Will Deacon <will@kernel.org>
+
+description: |
+  Firmware-initialised PCI host controllers and PCI emulations, such as the
+  virtio-pci implementations found in kvmtool and other para-virtualised
+  systems, do not require driver support for complexities such as regulator
+  and clock management. In fact, the controller may not even require the
+  configuration of a control interface by the operating system, instead
+  presenting a set of fixed windows describing a subset of IO, Memory and
+  Configuration Spaces.
+
+  Configuration Space is assumed to be memory-mapped (as opposed to being
+  accessed via an ioport) and laid out with a direct correspondence to the
+  geography of a PCI bus address by concatenating the various components to
+  form an offset.
+
+  For CAM, this 24-bit offset is:
+
+          cfg_offset(bus, device, function, register) =
+                     bus << 16 | device << 11 | function << 8 | register
+
+  While ECAM extends this by 4 bits to accommodate 4k of function space:
+
+          cfg_offset(bus, device, function, register) =
+                     bus << 20 | device << 15 | function << 12 | register
+
+  Interrupt mapping is exactly as described in `Open Firmware Recommended
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    description: Depends on the layout of configuration space (CAM vs ECAM
+      respectively). May also have more specific compatibles.
+    anyOf:
+      - description:
+          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
+        items:
+          - const: arm,juno-r1-pcie
+          - const: plda,xpressrich3-axi
+          - const: pci-host-ecam-generic
+      - description: |
+          ThunderX PCI host controller for pass-1.x silicon
+
+          Firmware-initialized PCI host controller to on-chip devices found on
+          some Cavium ThunderX processors.  These devices have ECAM-based config
+          access, but the BARs are all at fixed addresses.  We handle the fixed
+          addresses by synthesizing Enhanced Allocation (EA) capabilities for
+          these devices.
+        const: cavium,pci-host-thunder-ecam
+      - description: |
+          In some cases, firmware may already have configured the Synopsys
+          DesignWare PCIe controller in RC mode with static ATU window mappings
+          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
+          compatible fashion. In this case, there is no need for the OS to
+          perform any low level setup of clocks, PHYs or device registers, nor
+          is there any reason for the driver to reconfigure ATU windows for
+          config and/or IO space accesses at runtime.
+
+          In cases where the IP was synthesized with a minimum ATU window size
+          of 64 KB, it cannot be supported by the generic ECAM driver, because
+          it requires special config space accessors that filter accesses to
+          device #1 and beyond on the first bus.
+        items:
+          - enum:
+              - marvell,armada8k-pcie-ecam
+              - socionext,synquacer-pcie-ecam
+          - const: snps,dw-pcie-ecam
+      - contains:
+          enum:
+            - pci-host-cam-generic
+            - pci-host-ecam-generic
+
+  reg:
+    description:
+      The Configuration Space base address and size, as accessed from the parent
+      bus. The base address corresponds to the first bus in the "bus-range"
+      property. If no "bus-range" is specified, this will be bus 0 (the
+      default).
+    maxItems: 1
+
+  ranges:
+    description:
+      As described in IEEE Std 1275-1994, but must provide at least a
+      definition of non-prefetchable memory. One or both of prefetchable Memory
+      and IO Space may also be provided.
+    minItems: 1
+    maxItems: 3
+
+  dma-coherent:
+    description: The host controller bridges the AXI transactions into PCIe bus
+      in a manner that makes the DMA operations to appear coherent to the CPUs.
+
+required:
+  - compatible
+  - reg
+  - ranges
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: arm,juno-r1-pcie
+then:
+  required:
+    - dma-coherent
+
+examples:
+  - |
+
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@40000000 {
+            compatible = "pci-host-cam-generic";
+            device_type = "pci";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            bus-range = <0x0 0x1>;
+
+            // CPU_PHYSICAL(2)  SIZE(2)
+            reg = <0x0 0x40000000  0x0 0x1000000>;
+
+            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
+            ranges = <0x01000000 0x0 0x01000000  0x0 0x01000000  0x0 0x00010000>,
+                     <0x02000000 0x0 0x41000000  0x0 0x41000000  0x0 0x3f000000>;
+
+            #interrupt-cells = <0x1>;
+
+            // PCI_DEVICE(3)  INT#(1)  CONTROLLER(PHANDLE)  CONTROLLER_DATA(3)
+            interrupt-map = <   0x0 0x0 0x0  0x1  &gic  0x0 0x4 0x1>,
+                            < 0x800 0x0 0x0  0x1  &gic  0x0 0x5 0x1>,
+                            <0x1000 0x0 0x0  0x1  &gic  0x0 0x6 0x1>,
+                            <0x1800 0x0 0x0  0x1  &gic  0x0 0x7 0x1>;
+
+            // PCI_DEVICE(3)  INT#(1)
+            interrupt-map-mask = <0xf800 0x0 0x0  0x7>;
+        };
+    };
+...
diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt b/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
deleted file mode 100644
index f478874b79ce..000000000000
--- a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* ThunderX PCI host controller for pass-1.x silicon
-
-Firmware-initialized PCI host controller to on-chip devices found on
-some Cavium ThunderX processors.  These devices have ECAM-based config
-access, but the BARs are all at fixed addresses.  We handle the fixed
-addresses by synthesizing Enhanced Allocation (EA) capabilities for
-these devices.
-
-The properties and their meanings are identical to those described in
-host-generic-pci.txt except as listed below.
-
-Properties of the host controller node that differ from
-host-generic-pci.txt:
-
-- compatible     : Must be "cavium,pci-host-thunder-ecam"
-
-Example:
-
-	pcie@84b000000000 {
-		compatible = "cavium,pci-host-thunder-ecam";
-		device_type = "pci";
-		msi-parent = <&its>;
-		msi-map = <0 &its 0x30000 0x10000>;
-		bus-range = <0 31>;
-		#size-cells = <2>;
-		#address-cells = <3>;
-		#stream-id-cells = <1>;
-		reg = <0x84b0 0x00000000 0 0x02000000>;  /* Configuration space */
-		ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */
-	};
diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt
index f131faea3b7c..f3c87d55753b 100644
--- a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt
+++ b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt
@@ -3,11 +3,8 @@
 Firmware-initialized PCI host controller found on some Cavium
 ThunderX processors.
 
-The properties and their meanings are identical to those described in
-host-generic-pci.txt except as listed below.
-
-Properties of the host controller node that differ from
-host-generic-pci.txt:
+In addition to standard PCI host bridge properties, the following properties
+are required:
 
 - compatible     : Must be "cavium,pci-host-thunder-pem"
 
diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt
deleted file mode 100644
index f3f75bfb42bc..000000000000
--- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-* PLDA XpressRICH3-AXI host controller
-
-The PLDA XpressRICH3-AXI host controller can be configured in a manner that
-makes it compliant with the SBSA[1] standard published by ARM Ltd. For those
-scenarios, the host-generic-pci.txt bindings apply with the following additions
-to the compatible property:
-
-Required properties:
- - compatible: should contain "plda,xpressrich3-axi" to identify the IP used.
-
-
-[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/
diff --git a/MAINTAINERS b/MAINTAINERS
index 21f3393c36e3..3a5ddc0d530c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12434,7 +12434,7 @@ M:	Will Deacon <will@kernel.org>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/host-generic-pci.txt
+F:	Documentation/devicetree/bindings/pci/host-generic-pci.yaml
 F:	drivers/pci/controller/pci-host-common.c
 F:	drivers/pci/controller/pci-host-generic.c
 
-- 
2.20.1

Re: [PATCH 1/3] dt-bindings: PCI: Convert Arm Versatile binding to DT schema

[Linus Walleij]

On Sat, Nov 16, 2019 at 1:52 AM Rob Herring <robh@kernel.org> wrote:

> Convert the Arm Versatile PCI host binding to a DT schema.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Andrew Murray <andrew.murray@arm.com>
> Signed-off-by: Rob Herring <robh@kernel.org>

Thanks for doing this.
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Geert Uytterhoeven]

Hi Rob,

On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> Convert the generic PCI host binding to DT schema. The derivative Juno,
> PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> their compatible strings. The simplest way to convert those to
> schema is just add them into the common generic PCI host schema.
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Andrew Murray <andrew.murray@arm.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: David Daney <david.daney@cavium.com>
> Signed-off-by: Rob Herring <robh@kernel.org>

> index 515b2f9542e5..000000000000
> --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> +++ /dev/null

> -Example:
> -
> -    pcie1: pcie@7f000000 {
> -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> -        device_type = "pci";
> -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> -        bus-range = <0x0 0xe>;
> -        #address-cells = <3>;
> -        #size-cells = <2>;
> -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> -
> -        #interrupt-cells = <0x1>;
> -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded
SoCs, where all devices are mapped to a single interrupt.

However, schemas/pci/pci-bus.yaml says:

  interrupt-map-mask:
    items:
      - description: PCI high address cell
        minimum: 0
        maximum: 0xf800
      - description: PCI mid address cell
        const: 0
      - description: PCI low address cell
        const: 0
      - description: PCI IRQ cell
        minimum: 1
        maximum: 7

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

> -        interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;
> -        msi-map = <0x0 &its 0x0 0x10000>;
> -        dma-coherent;
> -    };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Bjorn Helgaas]

On Fri, Nov 15, 2019 at 06:52:40PM -0600, Rob Herring wrote:
> Convert the generic PCI host binding to DT schema. The derivative Juno,
> PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> their compatible strings. The simplest way to convert those to
> schema is just add them into the common generic PCI host schema.
> 
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Andrew Murray <andrew.murray@arm.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: David Daney <david.daney@cavium.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  .../bindings/pci/arm,juno-r1-pcie.txt         |  10 --
>  .../bindings/pci/designware-pcie-ecam.txt     |  42 -----
>  .../bindings/pci/hisilicon-pcie.txt           |   4 +-
>  .../bindings/pci/host-generic-pci.txt         | 101 ------------
>  .../bindings/pci/host-generic-pci.yaml        | 150 ++++++++++++++++++
>  .../bindings/pci/pci-thunder-ecam.txt         |  30 ----
>  .../bindings/pci/pci-thunder-pem.txt          |   7 +-
>  .../bindings/pci/plda,xpressrich3-axi.txt     |  12 --
>  MAINTAINERS                                   |   2 +-
>  9 files changed, 155 insertions(+), 203 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
>  delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
>  delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml
>  delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
>  delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
> ...

> +  Interrupt mapping is exactly as described in `Open Firmware Recommended
> +

I think there's some text missing here.

> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    description: Depends on the layout of configuration space (CAM vs ECAM
> +      respectively). May also have more specific compatibles.
> +    anyOf:
> +      - description:
> +          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
> +        items:
> +          - const: arm,juno-r1-pcie
> +          - const: plda,xpressrich3-axi
> +          - const: pci-host-ecam-generic
> +      - description: |
> +          ThunderX PCI host controller for pass-1.x silicon
> +
> +          Firmware-initialized PCI host controller to on-chip devices found on
> +          some Cavium ThunderX processors.  These devices have ECAM-based config
> +          access, but the BARs are all at fixed addresses.  We handle the fixed
> +          addresses by synthesizing Enhanced Allocation (EA) capabilities for
> +          these devices.
> +        const: cavium,pci-host-thunder-ecam
> +      - description: |
> +          In some cases, firmware may already have configured the Synopsys
> +          DesignWare PCIe controller in RC mode with static ATU window mappings
> +          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
> +          compatible fashion. In this case, there is no need for the OS to
> +          perform any low level setup of clocks, PHYs or device registers, nor
> +          is there any reason for the driver to reconfigure ATU windows for
> +          config and/or IO space accesses at runtime.
> +
> +          In cases where the IP was synthesized with a minimum ATU window size
> +          of 64 KB, it cannot be supported by the generic ECAM driver, because
> +          it requires special config space accessors that filter accesses to
> +          device #1 and beyond on the first bus.
> +        items:
> +          - enum:
> +              - marvell,armada8k-pcie-ecam
> +              - socionext,synquacer-pcie-ecam
> +          - const: snps,dw-pcie-ecam
> +      - contains:
> +          enum:
> +            - pci-host-cam-generic
> +            - pci-host-ecam-generic

I assume the description that talks about "Synopsys DesignWare" goes
with "pci-host-cam-generic" and "pci-host-ecam-generic"?  I hope there
can be generic controllers using non-Synopsys IP, but I don't know
quite how the description/items/contains parts are related.

> +  reg:
> +    description:
> +      The Configuration Space base address and size, as accessed from the parent
> +      bus. The base address corresponds to the first bus in the "bus-range"
> +      property. If no "bus-range" is specified, this will be bus 0 (the
> +      default).
> +    maxItems: 1
> +
> +  ranges:
> +    description:
> +      As described in IEEE Std 1275-1994, but must provide at least a
> +      definition of non-prefetchable memory. One or both of prefetchable Memory
> +      and IO Space may also be provided.
> +    minItems: 1
> +    maxItems: 3
> +
> +  dma-coherent:
> +    description: The host controller bridges the AXI transactions into PCIe bus
> +      in a manner that makes the DMA operations to appear coherent to the CPUs.

The "host-generic-pci.yaml" name sounds very generic, so I'm not quite
sure how to read "AXI" -- that sounds like a feature of a specific
platform?  I think "dma-coherent" itself is not platform-specific.

> +required:
> +  - compatible
> +  - reg
> +  - ranges
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: arm,juno-r1-pcie
> +then:
> +  required:
> +    - dma-coherent

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Rob Herring]

On Fri, Dec 13, 2019 at 2:28 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Nov 15, 2019 at 06:52:40PM -0600, Rob Herring wrote:
> > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > their compatible strings. The simplest way to convert those to
> > schema is just add them into the common generic PCI host schema.
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Andrew Murray <andrew.murray@arm.com>
> > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: David Daney <david.daney@cavium.com>
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> >  .../bindings/pci/arm,juno-r1-pcie.txt         |  10 --
> >  .../bindings/pci/designware-pcie-ecam.txt     |  42 -----
> >  .../bindings/pci/hisilicon-pcie.txt           |   4 +-
> >  .../bindings/pci/host-generic-pci.txt         | 101 ------------
> >  .../bindings/pci/host-generic-pci.yaml        | 150 ++++++++++++++++++
> >  .../bindings/pci/pci-thunder-ecam.txt         |  30 ----
> >  .../bindings/pci/pci-thunder-pem.txt          |   7 +-
> >  .../bindings/pci/plda,xpressrich3-axi.txt     |  12 --
> >  MAINTAINERS                                   |   2 +-
> >  9 files changed, 155 insertions(+), 203 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
> >  delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> >  delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt
> >  create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
> >  delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
> > ...
>
> > +  Interrupt mapping is exactly as described in `Open Firmware Recommended
> > +
>
> I think there's some text missing here.

Removed now. The schemas capture in constraints what the missing text
did in free-form.

> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    description: Depends on the layout of configuration space (CAM vs ECAM
> > +      respectively). May also have more specific compatibles.
> > +    anyOf:
> > +      - description:
> > +          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
> > +        items:
> > +          - const: arm,juno-r1-pcie
> > +          - const: plda,xpressrich3-axi
> > +          - const: pci-host-ecam-generic
> > +      - description: |
> > +          ThunderX PCI host controller for pass-1.x silicon
> > +
> > +          Firmware-initialized PCI host controller to on-chip devices found on
> > +          some Cavium ThunderX processors.  These devices have ECAM-based config
> > +          access, but the BARs are all at fixed addresses.  We handle the fixed
> > +          addresses by synthesizing Enhanced Allocation (EA) capabilities for
> > +          these devices.
> > +        const: cavium,pci-host-thunder-ecam
> > +      - description: |
> > +          In some cases, firmware may already have configured the Synopsys
> > +          DesignWare PCIe controller in RC mode with static ATU window mappings
> > +          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
> > +          compatible fashion. In this case, there is no need for the OS to
> > +          perform any low level setup of clocks, PHYs or device registers, nor
> > +          is there any reason for the driver to reconfigure ATU windows for
> > +          config and/or IO space accesses at runtime.
> > +
> > +          In cases where the IP was synthesized with a minimum ATU window size
> > +          of 64 KB, it cannot be supported by the generic ECAM driver, because
> > +          it requires special config space accessors that filter accesses to
> > +          device #1 and beyond on the first bus.
> > +        items:
> > +          - enum:
> > +              - marvell,armada8k-pcie-ecam
> > +              - socionext,synquacer-pcie-ecam
> > +          - const: snps,dw-pcie-ecam
> > +      - contains:
> > +          enum:
> > +            - pci-host-cam-generic
> > +            - pci-host-ecam-generic
>
> I assume the description that talks about "Synopsys DesignWare" goes
> with "pci-host-cam-generic" and "pci-host-ecam-generic"?

No, it's a catch all for all other cases.

I'll add a description to make the separation more clear. Using
'contains' here was leftover from when I initially kept the same
separate file structure. With it all combined to 1 schema, there's
really no need for that and it should be 'items' list instead. The
difference is we'll fail on 'compatible = "foo,bar-pci",
"pci-host-ecam-generic";' whereas that is valid for 'contains'.

> I hope there
> can be generic controllers using non-Synopsys IP, but I don't know
> quite how the description/items/contains parts are related.

The '-' are important. They separate each entry under the 'anyOf'.

There are a few besides the ones listed with quirks:

arch/arm/boot/dts/alpine.dtsi
arch/arm64/boot/dts/al/alpine-v2.dtsi
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
arch/arm64/boot/dts/arm/fvp-base-revc.dts
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
arch/xtensa/boot/dts/virt.dts

Some of these might actually be Synopsys. The entry for Synopsys is
only for the not quite compliant configured IP.

Note that 'pci-host-cam-generic' is unused at least by anything upstream.

>
> > +  reg:
> > +    description:
> > +      The Configuration Space base address and size, as accessed from the parent
> > +      bus. The base address corresponds to the first bus in the "bus-range"
> > +      property. If no "bus-range" is specified, this will be bus 0 (the
> > +      default).
> > +    maxItems: 1
> > +
> > +  ranges:
> > +    description:
> > +      As described in IEEE Std 1275-1994, but must provide at least a
> > +      definition of non-prefetchable memory. One or both of prefetchable Memory
> > +      and IO Space may also be provided.
> > +    minItems: 1
> > +    maxItems: 3
> > +
> > +  dma-coherent:
> > +    description: The host controller bridges the AXI transactions into PCIe bus
> > +      in a manner that makes the DMA operations to appear coherent to the CPUs.
>
> The "host-generic-pci.yaml" name sounds very generic, so I'm not quite
> sure how to read "AXI" -- that sounds like a feature of a specific
> platform? I think "dma-coherent" itself is not platform-specific.

Indeed. On second thought, just 'true' here is enough as we don't need
individual bindings to describe common properties over and over.

Rob

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Rob Herring]

On Thu, Dec 12, 2019 at 7:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Rob,
>
> On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > their compatible strings. The simplest way to convert those to
> > schema is just add them into the common generic PCI host schema.
> >
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Andrew Murray <andrew.murray@arm.com>
> > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: David Daney <david.daney@cavium.com>
> > Signed-off-by: Rob Herring <robh@kernel.org>
>
> > index 515b2f9542e5..000000000000
> > --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> > +++ /dev/null
>
> > -Example:
> > -
> > -    pcie1: pcie@7f000000 {
> > -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> > -        device_type = "pci";
> > -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> > -        bus-range = <0x0 0xe>;
> > -        #address-cells = <3>;
> > -        #size-cells = <2>;
> > -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> > -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> > -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> > -
> > -        #interrupt-cells = <0x1>;
> > -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
>
> An all-zeroes interrupt-map-mask seems to be very common on embedded
> SoCs, where all devices are mapped to a single interrupt.

Indeed.

> However, schemas/pci/pci-bus.yaml says:
>
>   interrupt-map-mask:
>     items:
>       - description: PCI high address cell
>         minimum: 0
>         maximum: 0xf800
>       - description: PCI mid address cell
>         const: 0
>       - description: PCI low address cell
>         const: 0
>       - description: PCI IRQ cell
>         minimum: 1
>         maximum: 7
>
> and thus complains about an all-zeroes mask, e.g.
>
>     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
> pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Now fixed.

Thanks,
Rob

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Geert Uytterhoeven]

Hi Rob,

On Tue, Dec 31, 2019 at 12:30 AM Rob Herring <robh@kernel.org> wrote:
> On Thu, Dec 12, 2019 at 7:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> > > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > > their compatible strings. The simplest way to convert those to
> > > schema is just add them into the common generic PCI host schema.
> > >
> > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > Cc: Andrew Murray <andrew.murray@arm.com>
> > > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: David Daney <david.daney@cavium.com>
> > > Signed-off-by: Rob Herring <robh@kernel.org>
> >
> > > index 515b2f9542e5..000000000000
> > > --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> > > +++ /dev/null
> >
> > > -Example:
> > > -
> > > -    pcie1: pcie@7f000000 {
> > > -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> > > -        device_type = "pci";
> > > -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> > > -        bus-range = <0x0 0xe>;
> > > -        #address-cells = <3>;
> > > -        #size-cells = <2>;
> > > -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> > > -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> > > -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> > > -
> > > -        #interrupt-cells = <0x1>;
> > > -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> >
> > An all-zeroes interrupt-map-mask seems to be very common on embedded
> > SoCs, where all devices are mapped to a single interrupt.
>
> Indeed.
>
> > However, schemas/pci/pci-bus.yaml says:
> >
> >   interrupt-map-mask:
> >     items:
> >       - description: PCI high address cell
> >         minimum: 0
> >         maximum: 0xf800
> >       - description: PCI mid address cell
> >         const: 0
> >       - description: PCI low address cell
> >         const: 0
> >       - description: PCI IRQ cell
> >         minimum: 1
> >         maximum: 7
> >
> > and thus complains about an all-zeroes mask, e.g.
> >
> >     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
> > pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1
>
> Now fixed.

Thank you, confirmed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Geert Uytterhoeven]

Hi Rob,

On Tue, Dec 31, 2019 at 9:23 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, Dec 31, 2019 at 12:30 AM Rob Herring <robh@kernel.org> wrote:
> > On Thu, Dec 12, 2019 at 7:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> > > > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > > > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > > > their compatible strings. The simplest way to convert those to
> > > > schema is just add them into the common generic PCI host schema.
> > > >
> > > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > > Cc: Andrew Murray <andrew.murray@arm.com>
> > > > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > > > Cc: Will Deacon <will@kernel.org>
> > > > Cc: David Daney <david.daney@cavium.com>
> > > > Signed-off-by: Rob Herring <robh@kernel.org>
> > >
> > > > index 515b2f9542e5..000000000000
> > > > --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> > > > +++ /dev/null
> > >
> > > > -Example:
> > > > -
> > > > -    pcie1: pcie@7f000000 {
> > > > -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> > > > -        device_type = "pci";
> > > > -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> > > > -        bus-range = <0x0 0xe>;
> > > > -        #address-cells = <3>;
> > > > -        #size-cells = <2>;
> > > > -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> > > > -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> > > > -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> > > > -
> > > > -        #interrupt-cells = <0x1>;
> > > > -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> > >
> > > An all-zeroes interrupt-map-mask seems to be very common on embedded
> > > SoCs, where all devices are mapped to a single interrupt.
> >
> > Indeed.
> >
> > > However, schemas/pci/pci-bus.yaml says:
> > >
> > >   interrupt-map-mask:
> > >     items:
> > >       - description: PCI high address cell
> > >         minimum: 0
> > >         maximum: 0xf800
> > >       - description: PCI mid address cell
> > >         const: 0
> > >       - description: PCI low address cell
> > >         const: 0
> > >       - description: PCI IRQ cell
> > >         minimum: 1
> > >         maximum: 7
> > >
> > > and thus complains about an all-zeroes mask, e.g.
> > >
> > >     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
> > > pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1
> >
> > Now fixed.
>
> Thank you, confirmed.

And with latest renesas-drivers, I started seeing:

    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:0: [0, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:1: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:2: [2048, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:3: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:4: [4096, 0, 0, 2] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:5: [5, 0, 113, 4] is too short

Looks like interrupt-map is split incorrectly: shouldn't each entry have 8
cells?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Rob Herring]

On Tue, Dec 31, 2019 at 7:31 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Rob,
>
> On Tue, Dec 31, 2019 at 9:23 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Dec 31, 2019 at 12:30 AM Rob Herring <robh@kernel.org> wrote:
> > > On Thu, Dec 12, 2019 at 7:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> > > > > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > > > > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > > > > their compatible strings. The simplest way to convert those to
> > > > > schema is just add them into the common generic PCI host schema.
> > > > >
> > > > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > > > Cc: Andrew Murray <andrew.murray@arm.com>
> > > > > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > > > > Cc: Will Deacon <will@kernel.org>
> > > > > Cc: David Daney <david.daney@cavium.com>
> > > > > Signed-off-by: Rob Herring <robh@kernel.org>
> > > >
> > > > > index 515b2f9542e5..000000000000
> > > > > --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> > > > > +++ /dev/null
> > > >
> > > > > -Example:
> > > > > -
> > > > > -    pcie1: pcie@7f000000 {
> > > > > -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> > > > > -        device_type = "pci";
> > > > > -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> > > > > -        bus-range = <0x0 0xe>;
> > > > > -        #address-cells = <3>;
> > > > > -        #size-cells = <2>;
> > > > > -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> > > > > -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> > > > > -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> > > > > -
> > > > > -        #interrupt-cells = <0x1>;
> > > > > -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> > > >
> > > > An all-zeroes interrupt-map-mask seems to be very common on embedded
> > > > SoCs, where all devices are mapped to a single interrupt.
> > >
> > > Indeed.
> > >
> > > > However, schemas/pci/pci-bus.yaml says:
> > > >
> > > >   interrupt-map-mask:
> > > >     items:
> > > >       - description: PCI high address cell
> > > >         minimum: 0
> > > >         maximum: 0xf800
> > > >       - description: PCI mid address cell
> > > >         const: 0
> > > >       - description: PCI low address cell
> > > >         const: 0
> > > >       - description: PCI IRQ cell
> > > >         minimum: 1
> > > >         maximum: 7
> > > >
> > > > and thus complains about an all-zeroes mask, e.g.
> > > >
> > > >     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
> > > > pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1
> > >
> > > Now fixed.
> >
> > Thank you, confirmed.
>
> And with latest renesas-drivers, I started seeing:
>
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:0: [0, 0, 0, 1] is too short
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:1: [5, 0, 113, 4] is too short
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:2: [2048, 0, 0, 1] is too short
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:3: [5, 0, 113, 4] is too short
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:4: [4096, 0, 0, 2] is too short
>     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> interrupt-map:5: [5, 0, 113, 4] is too short
>
> Looks like interrupt-map is split incorrectly: shouldn't each entry have 8
> cells?

That must be with a current dtc which now splits the array before each
phandle. That works for phandle+args, but not *-map properties. :( I
was trying to avoid a bunch of dts updates to add brackets. I think
for now, I'll just drop the interrupt-map size constraint. It's not
all that accurate anyways as it doesn't look at cell sizes.

Rob

Re: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema

[Geert Uytterhoeven]

Hi Rob,

On Tue, Dec 31, 2019 at 6:10 PM Rob Herring <robh@kernel.org> wrote:
> On Tue, Dec 31, 2019 at 7:31 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Dec 31, 2019 at 9:23 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Tue, Dec 31, 2019 at 12:30 AM Rob Herring <robh@kernel.org> wrote:
> > > > On Thu, Dec 12, 2019 at 7:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Sat, Nov 16, 2019 at 1:53 AM Rob Herring <robh@kernel.org> wrote:
> > > > > > Convert the generic PCI host binding to DT schema. The derivative Juno,
> > > > > > PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in
> > > > > > their compatible strings. The simplest way to convert those to
> > > > > > schema is just add them into the common generic PCI host schema.
> > > > > >
> > > > > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > > > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > > > > > Cc: Andrew Murray <andrew.murray@arm.com>
> > > > > > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > > > > > Cc: Will Deacon <will@kernel.org>
> > > > > > Cc: David Daney <david.daney@cavium.com>
> > > > > > Signed-off-by: Rob Herring <robh@kernel.org>
> > > > >
> > > > > > index 515b2f9542e5..000000000000
> > > > > > --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
> > > > > > +++ /dev/null
> > > > >
> > > > > > -Example:
> > > > > > -
> > > > > > -    pcie1: pcie@7f000000 {
> > > > > > -        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
> > > > > > -        device_type = "pci";
> > > > > > -        reg = <0x0 0x7f000000 0x0 0xf00000>;
> > > > > > -        bus-range = <0x0 0xe>;
> > > > > > -        #address-cells = <3>;
> > > > > > -        #size-cells = <2>;
> > > > > > -        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
> > > > > > -                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
> > > > > > -                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
> > > > > > -
> > > > > > -        #interrupt-cells = <0x1>;
> > > > > > -        interrupt-map-mask = <0x0 0x0 0x0 0x0>;
> > > > >
> > > > > An all-zeroes interrupt-map-mask seems to be very common on embedded
> > > > > SoCs, where all devices are mapped to a single interrupt.
> > > >
> > > > Indeed.
> > > >
> > > > > However, schemas/pci/pci-bus.yaml says:
> > > > >
> > > > >   interrupt-map-mask:
> > > > >     items:
> > > > >       - description: PCI high address cell
> > > > >         minimum: 0
> > > > >         maximum: 0xf800
> > > > >       - description: PCI mid address cell
> > > > >         const: 0
> > > > >       - description: PCI low address cell
> > > > >         const: 0
> > > > >       - description: PCI IRQ cell
> > > > >         minimum: 1
> > > > >         maximum: 7
> > > > >
> > > > > and thus complains about an all-zeroes mask, e.g.
> > > > >
> > > > >     arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:
> > > > > pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1
> > > >
> > > > Now fixed.
> > >
> > > Thank you, confirmed.
> >
> > And with latest renesas-drivers, I started seeing:
> >
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:0: [0, 0, 0, 1] is too short
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:1: [5, 0, 113, 4] is too short
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:2: [2048, 0, 0, 1] is too short
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:3: [5, 0, 113, 4] is too short
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:4: [4096, 0, 0, 2] is too short
> >     arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
> > interrupt-map:5: [5, 0, 113, 4] is too short
> >
> > Looks like interrupt-map is split incorrectly: shouldn't each entry have 8
> > cells?
>
> That must be with a current dtc which now splits the array before each
> phandle. That works for phandle+args, but not *-map properties. :( I

Ah, that explains it: renesas-drivers does include your for-next branch.
At first I was a bit puzzled, as the messages weren't introduced by a
dt-schema repo update...

> was trying to avoid a bunch of dts updates to add brackets. I think
> for now, I'll just drop the interrupt-map size constraint. It's not
> all that accurate anyways as it doesn't look at cell sizes.

Too late, I've already applied grouping to the Renesas ARM DTS files ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds