From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 267DAC433FE for ; Mon, 6 Dec 2021 19:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348134AbhLFTDe (ORCPT ); Mon, 6 Dec 2021 14:03:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237788AbhLFTDe (ORCPT ); Mon, 6 Dec 2021 14:03:34 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D94C7C061746; Mon, 6 Dec 2021 11:00:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A535AB811A3; Mon, 6 Dec 2021 19:00:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 74558C341C1; Mon, 6 Dec 2021 19:00:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638817202; bh=IMViehBOf0L+XbStK9Zjx1e5o+aABQ6NOVVz7Rc0EUk=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=XoiSiLFk4O2lmDFwFnxe1uCXF7uioAY/SFPauP2Ksik2tlKqfQ+iLc5sy+r7MByZy OgtQ740eMPidlLeN/i/C/w4zm86O8zp/peQghDcJtwj405kc+xCGr12pC8P3QOhFXV UoMEklWP3+Yr01aAvbKMQ1kWYXNFF+QtzPGvetxeABqVirL1ZBg/U0b0NzkYzG3+UA lGhmrzESXf/DHzNhzTaKUQh4BBoAP9C4Rg7Winy0CM/pauhW1yVsJHsX5FPEkqkkFy 4o/K1Tg7C2jaJsSls6zCRnL3RZ+LLcuvGTirOcAndrghXBflIZ5ok+2vyOJ709K5KB 21s7YUYT/t8PQ== Received: by mail-ed1-f49.google.com with SMTP id r11so46792488edd.9; Mon, 06 Dec 2021 11:00:02 -0800 (PST) X-Gm-Message-State: AOAM530g3ui/MFCfj02SA9pgdt8TiNuIj/N3RL19oG6iOEfaKi7ijFEq wlkTdYTZuwD4tHLKNNYJCm8AkKaCWgo1A1ZcAQ== X-Google-Smtp-Source: ABdhPJxGSuRINUCmm+jJXOgrMaUOzXgAy5KTBxSTt+mx1YjqsznGmtJq7Y4iUdoOmE5IJJxHpcxJOb26dgCHNE0ndeQ= X-Received: by 2002:a17:907:16ac:: with SMTP id hc44mr45661211ejc.363.1638817200749; Mon, 06 Dec 2021 11:00:00 -0800 (PST) MIME-Version: 1.0 References: <20211122103032.517923-1-maz@kernel.org> <8735no70tt.wl-maz@kernel.org> <87tug3clvc.wl-maz@kernel.org> <87r1b7ck40.wl-maz@kernel.org> <87tufvmes9.wl-maz@kernel.org> <87bl21mqwk.wl-maz@kernel.org> <87y24y112a.wl-maz@kernel.org> In-Reply-To: From: Rob Herring Date: Mon, 6 Dec 2021 12:59:48 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] of/irq: Add a quirk for controllers with their own definition of interrupt-map To: "Lad, Prabhakar" Cc: Marc Zyngier , Geert Uytterhoeven , Prabhakar Mahadev Lad , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "kernel-team@android.com" , John Crispin , Biwen Li , Chris Brandt , "linux-renesas-soc@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Dec 6, 2021 at 10:55 AM Lad, Prabhakar wrote: > > On Mon, Dec 6, 2021 at 10:26 AM Marc Zyngier wrote: > > > > On Sun, 05 Dec 2021 22:27:35 +0000, > > "Lad, Prabhakar" wrote: > > > > > > On Wed, Dec 1, 2021 at 4:16 PM Lad, Prabhakar > > > wrote: > > > > > > > > On Wed, Dec 1, 2021 at 2:36 PM Rob Herring wrote: > > > > > > > > > > On Wed, Dec 1, 2021 at 7:37 AM Lad, Prabhakar > > > > > wrote: > > > > > > > > > > > > Hi Marc/Rob, > > > > > > > > > > > > On Tue, Nov 30, 2021 at 6:37 PM Marc Zyngier wrote: > > > > > > > > > > > > > > On Tue, 30 Nov 2021 12:52:21 +0000, > > > > > > > "Lad, Prabhakar" wrote: > > > > > > > > > > > > > > > > On Mon, Nov 29, 2021 at 6:33 PM Rob Herring wrote: > > > > > > > > > > > > > > > > > > interrupts would work just fine here: > > > > > > > > > > > > > > > > > > interrupts = , > > > > > > > > > , > > > > > > > > > , > > > > > > > > > , > > > > > > > > > , > > > > > > > > > , > > > > > > > > > , > > > > > > > > > ; > > > > > > > > > > > > > > > > > > We don't need a different solution for N:1 interrupts from N:M. Sure, > > > > > > > > > that could become unweldy if there are a lot of interrupts (just like > > > > > > > > > interrupt-map), but is that an immediate problem? > > > > > > > > > > > > > > > > > It's just that with this approach the driver will have to index the > > > > > > > > interrupts instead of reading from DT. > > > > > > > > > > > > > > > > Marc - is it OK with the above approach? > > > > > > > > > > > > > > Anything that uses standard properties in a standard way works for me. > > > > > > > > > > > > > I added interrupts property now instead of interrupt-map as below: > > > > > > > > > > > > irqc: interrupt-controller@110a0000 { > > > > > > compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; > > > > > > #address-cells = <0>; > > > > > > interrupt-parent = <&gic>; > > > > > > interrupt-controller; > > > > > > reg = <0 0x110a0000 0 0x10000>; > > > > > > interrupts = > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > , > > > > > > ; > > > > > > clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, > > > > > > <&cpg CPG_MOD R9A07G044_IA55_PCLK>; > > > > > > clock-names = "clk", "pclk"; > > > > > > power-domains = <&cpg>; > > > > > > resets = <&cpg R9A07G044_IA55_RESETN>; > > > > > > }; > > > > > > > > > > > > > > > > > > In the hierarchal interrupt code its parsed as below: > > > > > > on probe fetch the details: > > > > > > range = of_get_property(np, "interrupts", &len); > > > > > > if (!range) > > > > > > return -EINVAL; > > > > > > > > > > > > for (len /= sizeof(*range), j = 0; len >= 3; len -= 3) { > > > > > > if (j >= IRQC_NUM_IRQ) > > > > > > return -EINVAL; > > > > > > > > > > > > priv->map[j].args[0] = be32_to_cpu(*range++); > > > > > > priv->map[j].args[1] = be32_to_cpu(*range++); > > > > > > priv->map[j].args[2] = be32_to_cpu(*range++); > > > > > > priv->map[j].args_count = 3; > > > > > > j++; > > > > > > > > > > Not sure what's wrong, but you shouldn't be doing your own parsing. > > > > > The setup shouldn't look much different than a GPIO controller > > > > > interrupts except you have multiple parent interrupts. > > > > > > > > > Sorry does that mean the IRQ domain should be chained handler and not > > > > hierarchical? Or is it I have miss-understood. > > > > I guess the core DT code allocates the interrupts itself, as if the > > interrupt controller was the interrupt producer itself (which isn't > > the case here), bypassing the hierarchical setup altogether. > > > > We solved it on the MSI side by not using 'interrupts'. Either we > > adopt a similar solution for wired interrupts, or we fix the core DT > > code. > > > So maybe for now we go with your earlier suggestion of using > "interrupt-range"? (And address the core DT in near future) > > Rob, is that OK with you? No. The existing bindings are sufficient for describing what you need to describe. If the kernel can't handle that, that's no reason for a new binding. The core code needs to handle all this whether it's 'interrupts' or 'interrupt-range' you are parsing. Sorry, but I really don't understand the hierarchical stuff to provide better guidance. Rob