From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 393A6C2D0DC for ; Thu, 2 Jan 2020 16:34:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0D15120866 for ; Thu, 2 Jan 2020 16:34:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="gelJmfqD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728822AbgABQew (ORCPT ); Thu, 2 Jan 2020 11:34:52 -0500 Received: from mail-io1-f66.google.com ([209.85.166.66]:44019 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728808AbgABQew (ORCPT ); Thu, 2 Jan 2020 11:34:52 -0500 Received: by mail-io1-f66.google.com with SMTP id n21so37227340ioo.10 for ; Thu, 02 Jan 2020 08:34:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=n02NZb1q13MC+D+YIZeKacRc8gevOmHNy1haOLJb4io=; b=gelJmfqDyUmjwBH/XMMX/bBXaKDVC6YTmAj8rPELVV13MZipjbHUb7JPhFkSuDop1U ByiLKjmlDBsd8mhMeRa6Is5L7PN0Wzk2rxFBkZqRfzxyPP1Bgn9Y5J2iih8/libglJ22 dOtjW3gXu4mZCdjaMzxLU4AnQWrng2RGMawBo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=n02NZb1q13MC+D+YIZeKacRc8gevOmHNy1haOLJb4io=; b=seDI8tKqYv7WirhI8ZwHz2N2GS6h2DbFidNI5hSe5TPIDER2cGtXaZqbLRSfleFnSW 6JzXOQ1j5oRJNOO46mYT4DvA0gqJge2xgY1YWGLTEfI6LMASGnWUMz2wPueO/uqfqWX6 4+OePA+dwOvdEawc8QLMij0a7W9ntLGaHrrVK0wMX1wQfzxvtbn+v7fkRNEvmFo1JJXE yAKn1LbeZzLCS5Duvb7dX39v/hEgzWmMZsv9a0rU7L75VQHi4lTIyo1pnx+nhItgSucS 4/mSCs9ZsCAr0RSDRCA6V1uomjlLvded0GYjWuGAhl/ECsh7zlDBzDnfKRb1oouECsEq 5fHA== X-Gm-Message-State: APjAAAV5WtfNf4MO0oXELyuZjEMRgon6LDWsa1IqChNGQ5cJ53oUPpDJ OLSm3h4HBnsroRKKKbx0XTr/v0amVqwSJXogzVI7WQ== X-Google-Smtp-Source: APXvYqz8y/GovnsF0D2tm3lNOpYaS0G7+35htjGwpcyBgB9MdOWIe9CYMW8Ole+deE4SlX9aakNc01/kDuMb4EgOvMg= X-Received: by 2002:a02:b897:: with SMTP id p23mr67001302jam.58.1577982891338; Thu, 02 Jan 2020 08:34:51 -0800 (PST) MIME-Version: 1.0 References: <20191231130528.20669-1-jagan@amarulasolutions.com> <20191231130528.20669-3-jagan@amarulasolutions.com> <20200102105424.kmte7aooh2gkrcnu@gilmour.lan> <20200102154703.3prgwcjyo36g5g5u@gilmour.lan> In-Reply-To: <20200102154703.3prgwcjyo36g5g5u@gilmour.lan> From: Jagan Teki Date: Thu, 2 Jan 2020 22:04:40 +0530 Message-ID: Subject: Re: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40 To: Maxime Ripard Cc: Chen-Yu Tsai , Jernej Skrabec , Rob Herring , David Airlie , Daniel Vetter , Mark Rutland , dri-devel , linux-arm-kernel , linux-kernel , devicetree , linux-sunxi , linux-amarula Content-Type: text/plain; charset="UTF-8" Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jan 2, 2020 at 9:17 PM Maxime Ripard wrote: > > On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote: > > On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote: > > > > > > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote: > > > > TCON LCD0, LCD1 in allwinner R40, are used for managing > > > > LCD interfaces like RGB, LVDS and DSI. > > > > > > > > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via > > > > tcon top. > > > > > > > > Add support for it, in tcon driver. > > > > > > > > Signed-off-by: Jagan Teki > > > > --- > > > > Changes for v3: > > > > - none > > > > > > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 8 ++++++++ > > > > 1 file changed, 8 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > > index fad72799b8df..69611d38c844 100644 > > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > > @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { > > > > .has_channel_1 = true, > > > > }; > > > > > > > > +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = { > > > > + .supports_lvds = true, > > > > + .has_channel_0 = true, > > > > + /* TODO Need to support TCON output muxing via GPIO pins */ > > > > + .set_mux = sun8i_r40_tcon_tv_set_mux, > > > > > > What is this muking about? And why is it a TODO? > > > > Muxing similar like how TCON TOP handle TV0, TV1 I have reused the > > same so-that it would configure de port selection via > > sun8i_tcon_top_de_config > > > > TCON output muxing have gpio with GPIOD and GPIOH bits, which select > > which of LCD or TV TCON outputs to the LCD function pins. I have > > marked these has TODO for further support as mentioned by Chen-Yu in > > v1[1]. > > It should be in the commit log. Make sense. > > What's the plan to support that when needed? And that means that the > LCD and TV outputs are mutually exclusive? We should at the very least > check that both aren't enabled at the same time. Yes, LCD or TV within the outselect seems to be mutually exclusive. Like LCD0 or TV0 can output to GPIOD incase of TV0_OUTSEL and LCD1 or TV1 can output to GPIOH incase of TV1_OUTSEL. I think checking them before configuring TCON_TOP_PORT_SEL_REG would make sense, let me know if you have any suggestions?