From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8639AC433F5 for ; Fri, 7 Oct 2022 03:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229487AbiJGDve (ORCPT ); Thu, 6 Oct 2022 23:51:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbiJGDvd (ORCPT ); Thu, 6 Oct 2022 23:51:33 -0400 Received: from mail-oa1-x29.google.com (mail-oa1-x29.google.com [IPv6:2001:4860:4864:20::29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F1D5BE2CC for ; Thu, 6 Oct 2022 20:51:32 -0700 (PDT) Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-132af5e5543so4371540fac.8 for ; Thu, 06 Oct 2022 20:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ywOJjC1iAeM1WckDzdDR6XJ9UsRidM3rIQ+Y2hJNDKM=; b=Cm8A2XN+mF9SQCfZ8U83Xr2/sdIj3A4gzywnUW/7Rg8Ps6TUj4mhzqhCDtGqP7rbCX cR0e5rS0OPRwXdYsVNItxkjYH46iUD/Bd/+KUmlHvltKz67cwSfZ1QPHMg10zi1Iw9bm vDZbb+QvIf3iyYRqE/pS19gScSSw1GkfnatsP8vKo8rbOgn6RPhSaNJX1B1SkuM2/vq7 1ro4NazkBLM0NjJ1s+DFBjBdE1QhYGBWWpOMpKVLCIXLv5L9XAAnJtiRU9u+E/g+SHEl qm19+eysnC3NebtYzE6Z6Mi6JCPSiZIIXR689VTSW5J1/AfsM2qmJLQlgJZEeJllTKHy aB6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ywOJjC1iAeM1WckDzdDR6XJ9UsRidM3rIQ+Y2hJNDKM=; b=bFl1OM07roihkG3zfsQQwyOiPiO5GcftjFk1mu+IkjXXJ8/GsKioUp94AzKjGBTmJ/ S3o3h4mBM+pKQBeJOLrSM4BGvAhssGCpkxkaCBKg+7M5mJeUb6bfz+7Xzn1w0jGzgHxT DhkHCTZtDixjdBMG8WacVt7x6ZvWUZIthaIBj0n5yJi2kBcGCFwH8N/HJw2uGZhmCNqI Nd02ZyaOESUoewZzkf2MAKsX1C04xiqa3nnc5r+Ds2DEfRuE27dQuZo7sJypYwTpbgPP 4XTWB49QGLgQmrtb8pIAJIwQlPVew89VKFsB33u6Ny1SW17PXNJMNlJQJ9Ffbxt5bA9M lGLQ== X-Gm-Message-State: ACrzQf0O2SYQZxZeucPNb9WjdvuZayXu+CLUJXSLXV8N0eSNUTb1sTLu b+9hckcV3AIdSXWpw3psWykuF0492ALECwdBFMcPqQPvMZtFmg== X-Google-Smtp-Source: AMsMyM58r3x61gcQz490WPKR8f7M4ASa5M+2B+LqM+DSCDhS6Ek4QKEKnabKgdcccswhnXNdVIOArInEoUBb8fej4mo= X-Received: by 2002:a05:6870:ac21:b0:132:f716:1804 with SMTP id kw33-20020a056870ac2100b00132f7161804mr4707931oab.248.1665114691420; Thu, 06 Oct 2022 20:51:31 -0700 (PDT) MIME-Version: 1.0 References: <20220829062202.3287-2-zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Fri, 7 Oct 2022 11:51:20 +0800 Message-ID: Subject: Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache To: Palmer Dabbelt Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, Paul Walmsley , aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Oct 7, 2022 at 10:58 AM Palmer Dabbelt wrote: > > On Sun, 28 Aug 2022 23:22:00 PDT (-0700), zong.li@sifive.com wrote: > > Since composible cache may be L3 cache if private L2 cache exists, it > > should use its original name composible cache to prevent confusion. > > > > Signed-off-by: Greentime Hu > > Signed-off-by: Zong Li > > --- > > .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%) > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml > > similarity index 92% > > rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml > > index 69cdab18d629..1a64a5384e36 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml > > @@ -12,8 +12,8 @@ maintainers: > > - Paul Walmsley > > > > description: > > - The SiFive Level 2 Cache Controller is used to provide access to fast copies > > - of memory for masters in a Core Complex. The Level 2 Cache Controller also > > + The SiFive Composable Cache Controller is used to provide access to fast copies > > + of memory for masters in a Core Complex. The Composable Cache Controller also > > acts as directory-based coherency manager. > > All the properties in ePAPR/DeviceTree specification applies for this platform. > > > > @@ -27,6 +27,7 @@ select: > > enum: > > - sifive,fu540-c000-ccache > > - sifive,fu740-c000-ccache > > + - sifive,ccache0 > > Looks like Rob's bot had comments and I don't see a v2. Sorry if I'm > missing something. Hi Palmer, We moved this series to the following patch set: http://lists.infradead.org/pipermail/linux-riscv/2022-October/020196.html Sorry for the confusion. Many thanks for considering this series. > > Also: I'd guess that we only had the SOC-specific mappings on purpose. > It's kind of a grey area and I'm OK either way, but I'd definately > prefer the DT folks to get a chance to review these. My guess is that > they're not looking due to the bot comments, but sorry again if I've > missed it. > > > required: > > - compatible > > @@ -37,6 +38,7 @@ properties: > > - enum: > > - sifive,fu540-c000-ccache > > - sifive,fu740-c000-ccache > > + - sifive,ccache0 > > - const: cache > > > > cache-block-size: