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Wed, 11 Nov 2020 06:45:41 -0500 Received: from mail-vk1-xa42.google.com (mail-vk1-xa42.google.com [IPv6:2607:f8b0:4864:20::a42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDE98C0613D6 for ; Wed, 11 Nov 2020 03:45:39 -0800 (PST) Received: by mail-vk1-xa42.google.com with SMTP id q77so416827vkq.1 for ; Wed, 11 Nov 2020 03:45:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=W2LROEDqwB/YAfpZuvnNBx/s/n4ussPUTp1SoV848WE=; b=Rj4QLbP7hQUGidksqh3Sz+Mz1awLgghgywmgmq9iaGhu6djYI966xmN5JUcRmcYrq/ Woc2NSWg8j33913hx6Vmfrrzuym6+skblcbvL41IiQFacYFt1SjAs/nslFk+g3W36u4V 5Z4diCxFrS93BVrqJ7SDLPJfjdeswkTya8vvZmjaKgR3zhBTTE1EhWuFIHUSn9N1wPo1 iX4p8Jc2fBB3F1mpe8ZqM6XFLIoz2+OX+tvgiLg3x8tn5z0hkeUvi4fzbnv3qjZga/O9 dv9NoC5jp/yLI8jF8N3x1Yw2xoMv3ppOhpBWH3CIkWAXgT5hobFLAqPh/q8PjOiT3/Eo yovw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=W2LROEDqwB/YAfpZuvnNBx/s/n4ussPUTp1SoV848WE=; b=SmO8wBi61bdsHO+XF/nbK0s15YvNWezD9XZcmaYKvRvRgeKeIgzdYQdIesTeLr1iXN uIKtgqx9qI7RoIPvMR9ztmywNsPWbRTgdNgbpgycJTBg0IftX57taBf0m8jFBNz7yGAJ w03LfV1zsp+HGZqxuFB3BWgS+gWaaQ3qXRNbFzNQi9oxWzbJjzFh+SQ7IeErWh6TkmxY JSGTSuFl0intjCOo6DJIw2qJnxhN0LzDYel9n891PFhAgx5TW5bbJ1MVBbTrdAZz5Ccb JkSFrqXcgCnNOKaeFOEmzmbOoILqeOC1uWa1rlkuTSq+b04QW1e+3FQgJbDbkuBEepwM Y5DQ== X-Gm-Message-State: AOAM5311GvFkqluJXtV+abb99apA1vT1YKJXzvORqCJvTreYmvR1N8Uj xqvXW5M5MmhV4VixzeJysNAO0FXAHcfvDIZ4UwrHWA== X-Google-Smtp-Source: ABdhPJy49vZO4pNDp6JtJUn+KdVv0aND0NyO3da5g+cVxXyOVmgGe9S4bf/F/v98cY0CP0i1NrbPCyiERv3WhWMkEBU= X-Received: by 2002:a1f:41cc:: with SMTP id o195mr13053486vka.15.1605095138861; Wed, 11 Nov 2020 03:45:38 -0800 (PST) MIME-Version: 1.0 References: <20201104234427.26477-1-digetx@gmail.com> <20201104234427.26477-2-digetx@gmail.com> In-Reply-To: <20201104234427.26477-2-digetx@gmail.com> From: Ulf Hansson Date: Wed, 11 Nov 2020 12:45:02 +0100 Message-ID: Subject: Re: [PATCH v1 01/30] dt-bindings: host1x: Document OPP and voltage regulator properties To: Dmitry Osipenko , Rob Herring Cc: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Mauro Carvalho Chehab , Marek Szyprowski , Peter Geis , Nicolas Chauvet , linux-samsung-soc , driverdevel , Linux USB List , linux-pwm@vger.kernel.org, "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , DTML , dri-devel , Linux Media Mailing List , linux-tegra Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 5 Nov 2020 at 00:44, Dmitry Osipenko wrote: > > Document new DVFS OPP table and voltage regulator properties of the > Host1x bus and devices sitting on the bus. > > Signed-off-by: Dmitry Osipenko > --- > .../display/tegra/nvidia,tegra20-host1x.txt | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > index 34d993338453..0593c8df70bb 100644 > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > @@ -20,6 +20,18 @@ Required properties: > - reset-names: Must include the following entries: > - host1x > > +Optional properties: > +- operating-points-v2: See ../bindings/opp/opp.txt for details. > +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. > + > +For each opp entry in 'operating-points-v2' table of host1x and its modules: > +- opp-supported-hw: One bitfield indicating: > + On Tegra20: SoC process ID mask > + On Tegra30+: SoC speedo ID mask > + > + A bitwise AND is performed against the value and if any bit > + matches, the OPP gets enabled. > + > Each host1x client module having to perform DMA through the Memory Controller > should have the interconnect endpoints set to the Memory Client and External > Memory respectively. > @@ -45,6 +57,8 @@ of the following host1x client modules: > - interconnect-names: Must include name of the interconnect path for each > interconnect entry. Consult TRM documentation for information about > available memory clients, see MEMORY CONTROLLER section. > + - core-supply: Phandle of voltage regulator of the SoC "core" power domain. > + - operating-points-v2: See ../bindings/opp/opp.txt for details. > As discussed in the thread for the cover-letter. We already have DT bindings for power-domains (providers and consumers). Please use them instead of adding SoC specific bindings to each peripheral device. [...] Kind regards Uffe