From: Yash Shah <yash.shah@sifive.com>
To: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: "robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"bmeng.cn@gmail.com" <bmeng.cn@gmail.com>,
"allison@lohutok.net" <allison@lohutok.net>,
"alexios.zavras@intel.com" <alexios.zavras@intel.com>,
Atish Patra <Atish.Patra@wdc.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
Greg KH <gregkh@linuxfoundation.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
Date: Mon, 23 Dec 2019 08:53:20 +0000 [thread overview]
Message-ID: <CH2PR13MB3368B844DB765AE9166C1F1A8C2E0@CH2PR13MB3368.namprd13.prod.outlook.com> (raw)
In-Reply-To: <mhng-a1ba4b8a-4c6a-43e9-a87a-f8bbbe3555d8@palmerdabbelt-glaptop>
> -----Original Message-----
> From: Palmer Dabbelt <palmerdabbelt@google.com>
> Sent: 14 December 2019 07:43
> To: Yash Shah <yash.shah@sifive.com>
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu;
> bmeng.cn@gmail.com; allison@lohutok.net; alexios.zavras@intel.com; Atish
> Patra <Atish.Patra@wdc.com>; tglx@linutronix.de; Greg KH
> <gregkh@linuxfoundation.org>; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Yash Shah
> <yash.shah@sifive.com>
> Subject: Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2
> cache way enabled
>
> On Mon, 09 Dec 2019 03:25:06 PST (-0800), yash.shah@sifive.com wrote:
> > In order to determine the number of L2 cache ways enabled at runtime,
> > implement a private attribute using cache_get_priv_group() in
> > cacheinfo framework. Reading this attribute
> ("number_of_ways_enabled")
> > will return the number of enabled L2 cache ways at runtime.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> > arch/riscv/include/asm/sifive_l2_cache.h | 2 ++
> > arch/riscv/kernel/cacheinfo.c | 31
> +++++++++++++++++++++++++++++++
> > drivers/soc/sifive/sifive_l2_cache.c | 5 +++++
> > 3 files changed, 38 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> > b/arch/riscv/include/asm/sifive_l2_cache.h
> > index 04f6748..217a42f 100644
> > --- a/arch/riscv/include/asm/sifive_l2_cache.h
> > +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> > @@ -10,6 +10,8 @@
> > extern int register_sifive_l2_error_notifier(struct notifier_block
> > *nb); extern int unregister_sifive_l2_error_notifier(struct
> > notifier_block *nb);
> >
> > +int sifive_l2_largest_wayenabled(void);
>
> I thought the plan was to get this stuff out of arch/riscv? It looks like it only
> got half-way done.
Are you suggesting to move this header file out of "/arch/riscv/include/asm/" to maybe "include/soc/sifive/"?
- Yash
next prev parent reply other threads:[~2019-12-23 8:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2019-12-14 2:12 ` Palmer Dabbelt
2019-12-15 19:56 ` Paul Walmsley
2019-12-23 8:53 ` Yash Shah [this message]
2019-12-14 2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
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