* [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8
@ 2018-02-01 18:31 Lucas Stach
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-23 14:56 ` [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8 Shawn Guo
0 siblings, 2 replies; 31+ messages in thread
From: Lucas Stach @ 2018-02-01 18:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
Add basic Kconfig symbols to make the MXC architecture available
in the ARM64 world.
Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
---
v2: fix "enabled" typo.
---
arch/arm64/Kconfig.platforms | 6 ++++++
drivers/soc/imx/Kconfig | 12 ++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2401373565ff..ae3be0d2cdb5 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -131,6 +131,12 @@ config ARCH_MVEBU
- Armada 7K SoC Family
- Armada 8K SoC Family
+config ARCH_MXC
+ bool "ARMv8 based NXP i.MX SoC family"
+ help
+ This enables support for the ARMv8 based SoCs in the
+ NXP i.MX family.
+
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
index a5b86a28f343..8c9f04440896 100644
--- a/drivers/soc/imx/Kconfig
+++ b/drivers/soc/imx/Kconfig
@@ -8,3 +8,15 @@ config IMX7_PM_DOMAINS
default y if SOC_IMX7D
endmenu
+
+if ARCH_MXC
+
+if ARM64
+
+config SOC_IMX8MQ
+ bool "i.MX8MQ support"
+ help
+ This enables support for the i.MX8MQ SoC.
+endif
+
+endif
--
2.15.1
--
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-01 18:31 ` Lucas Stach
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
` (2 more replies)
2018-02-01 18:31 ` [PATCH v2 3/4] arm64: add support for i.MX8M EVK board Lucas Stach
2018-02-01 18:31 ` [PATCH v2 4/4] MAINTAINERS: add i.MX8 DT path to i.MX architecture Lucas Stach
2 siblings, 3 replies; 31+ messages in thread
From: Lucas Stach @ 2018-02-01 18:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
This adds the basic DTS for the i.MX8MQ.
For now only the following peripherals are supported:
- IOMUXC (pin controller)
- CCM (clock controller)
- GPIO
- UART
- uSDHC (SD/eMMC controller)
- FEC (ethernet controller)
- i2c
This is enough to get a very basic board support up and running.
One known limitation is that the driver for the GPC interrupt
controller is still missing, rendering the CPU sleep states unusable
as there is nothing waking them up anymore. This will be fixed in
due course.
Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
v2:
- move to freescale folder
- change compatibles to "fsl" vendor prefix
- remove unnecessary newlines
- move status property to be the last in all node
- remove imx21 compatibles from UART nodes
- document compatible
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 +
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++
3 files changed, 1038 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index cdb9dd705754..85d1c9ec6fa3 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -75,6 +75,10 @@ i.MX6q generic board
Required root node properties:
- compatible = "fsl,imx6q";
+i.MX8MQ generic board
+Required root node properties:
+ - compatible = "fsl,imx8mq";
+
Freescale Vybrid Platform Device Tree Bindings
----------------------------------------------
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
new file mode 100644
index 000000000000..b94b02080a34
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __DTS_IMX8MQ_PINFUNC_H
+#define __DTS_IMX8MQ_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
+
+#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
new file mode 100644
index 000000000000..50ed302d299a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ */
+
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx8mq-pinfunc.h"
+
+/* first 128 KiB of memory are owned by ATF */
+/memreserve/ 0x40000000 0x00020000;
+
+/ {
+ /* This should really be the GPC, but we need a driver for this first */
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ };
+
+ ckil: clk-ckil {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc_25m: clk-osc-25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "osc_25m";
+ };
+
+ osc_27m: clk-osc-27m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc_27m";
+ };
+
+ clk_ext1: clk-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clk-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext2";
+ };
+
+ clk_ext3: clk-ext3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext3";
+ };
+
+ clk_ext4: clk-ext4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <133000000>;
+ clock-output-names = "clk_ext4";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&A53_L2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ clock-frequency = <8333333>;
+ interrupt-parent = <&gic>;
+ arm,no-tick-in-suspend;
+ };
+
+ peripherals@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x3e000000>;
+
+ bus@30000000 { /* AIPS1 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30000000 0x30000000 0x400000>;
+
+ gpio1: gpio@30200000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@30210000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30210000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@30220000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30220000 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@30230000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30230000 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@30240000 {
+ compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+ reg = <0x30240000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ iomuxc: iomuxc@30330000 {
+ compatible = "fsl,imx8mq-iomuxc";
+ reg = <0x30330000 0x10000>;
+ };
+
+ gpr: iomuxc-gpr@30340000 {
+ compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+ reg = <0x30340000 0x10000>;
+ };
+
+ anatop: anatop@30360000 {
+ compatible = "fsl,imx8mq-anatop", "syscon";
+ reg = <0x30360000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clk: clock-controller@30380000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
+ <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "ckil", "osc_25m", "osc_27m",
+ "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+ };
+
+ bus@30400000 { /* AIPS2 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30400000 0x30400000 0x400000>;
+ };
+
+ bus@30800000 { /* AIPS3 */
+ compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x30800000 0x30800000 0x400000>;
+
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
+ <&clk IMX8MQ_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
+ <&clk IMX8MQ_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
+ <&clk IMX8MQ_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c1: i2c@30a20000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a20000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@30a30000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a30000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@30a40000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a40000 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@30a50000 {
+ compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+ reg = <0x30a50000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart4: serial@30a60000 {
+ compatible = "fsl,imx8mq-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
+ <&clk IMX8MQ_CLK_UART4_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ usdhc1: usdhc@30b40000 {
+ compatible = "fsl,imx8mq-usdhc",
+ "fsl,imx7d-usdhc";
+ reg = <0x30b40000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC1_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc@30b50000 {
+ compatible = "fsl,imx8mq-usdhc",
+ "fsl,imx7d-usdhc";
+ reg = <0x30b50000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_USDHC2_ROOT>;
+ clock-names = "ipg", "ahb", "per";
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step = <2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ fec1: ethernet@30be0000 {
+ compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+ reg = <0x30be0000 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET1_ROOT>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+ <&clk IMX8MQ_CLK_ENET_REF_DIV>,
+ <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@38800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x38800000 0x10000>, /* GIC Dist */
+ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+ };
+};
--
2.15.1
--
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-01 18:31 ` [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
@ 2018-02-01 18:31 ` Lucas Stach
[not found] ` <20180201183126.32384-3-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-23 15:03 ` Shawn Guo
2018-02-01 18:31 ` [PATCH v2 4/4] MAINTAINERS: add i.MX8 DT path to i.MX architecture Lucas Stach
2 siblings, 2 replies; 31+ messages in thread
From: Lucas Stach @ 2018-02-01 18:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
This is the evaluation kit board for the i.MX8M. The current level of
support yields a working console and is able to boot userspace from
SD card or Network.
Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> (v1)
Tested-by: Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> (v1)
---
v2:
- move to freescale folder
- fix indentation
- fix typo in Makefile
- document compatible
- switch to generic pinconf
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 405 ++++++++++++++++++++++++++
3 files changed, 411 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-evk.dts
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 85d1c9ec6fa3..fd167203ad5f 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX8MQ Evaluation Kit
+Required root node properties:
+ - compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
Generic i.MX boards
-------------------
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18adb695a..85f96ae127c2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+
+dtb-$(CONFIG_SOC_IMX8MQ) += imx8mq-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
new file mode 100644
index 000000000000..c0e5ee5d6243
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "NXP i.MX8MQ EVK";
+ compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0xc0000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-vsd-3v3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2>;
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1_mdc>, <&pinctrl_fec1_mdio>,
+ <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
+ <&pinctrl_fec1_phy_reset>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x8>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3ab {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <975000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1675000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1625000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3625000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
+ <&pinctrl_usdhc1_data>;
+ pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
+ <&pinctrl_usdhc1_clk_strobe_100mhz>,
+ <&pinctrl_usdhc1_data_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
+ <&pinctrl_usdhc1_clk_strobe_200mhz>,
+ <&pinctrl_usdhc1_data_200mhz>;
+ vqmmc-supply = <&sw4_reg>;
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk>,
+ <&pinctrl_usdhc2_data>;
+ pinctrl-1 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_100mhz>,
+ <&pinctrl_usdhc2_data_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_200mhz>,
+ <&pinctrl_usdhc2_data_200mhz>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1_mdc: fec1mdcgrp {
+ pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_fec1_mdio: fec1mdiogrp {
+ pinmux = <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ drive-open-drain;
+ };
+
+ pinctrl_fec1_phy_reset: fec1phyresetgrp {
+ pinmux = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_fec1_data_tx: fec1datatxgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_fec1_data_rx: fec1datarxgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
+ >;
+ drive-strength = <1>;
+ slew-rate = <2>;
+ input-schmitt-enable;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ pinmux = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
+ >;
+ drive-strength = <7>;
+ slew-rate = <0>;
+ drive-open-drain;
+ input-enable;
+ };
+
+ pinctrl_reg_usdhc2: regusdhc2grpgpio {
+ pinmux = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_uart1: uart1grp {
+ pinmux = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
+ >;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc1_cd_reset: usdhc1cdgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
+ >;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc1_clk_strobe: usdhc1clkgrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc1_data: usdhc1datagrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc1_clk_strobe_100mhz: usdhc1clk100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc1_data_100mhz: usdhc1data100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc1_clk_strobe_200mhz: usdhc1clk200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_usdhc1_data_200mhz: usdhc1data200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_vselect: usdhc2vselectgrp {
+ pinmux = <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT>;
+ drive-strength = <1>;
+ slew-rate = <0>;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc2_clk: usdhc2clkgrp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ };
+
+ pinctrl_usdhc2_data: usdhc2datagrp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <3>;
+ slew-rate = <0>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_clk_100mhz: usdhc2clk100grp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ };
+
+ pinctrl_usdhc2_data_100mhz: usdhc2data100grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <5>;
+ slew-rate = <1>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ pinctrl_usdhc2_clk_200mhz: usdhc2clk200grp {
+ pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ };
+
+ pinctrl_usdhc2_data_200mhz: usdhc2data200grp {
+ pinmux = <
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+ >;
+ drive-strength = <7>;
+ slew-rate = <3>;
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+};
--
2.15.1
--
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 4/4] MAINTAINERS: add i.MX8 DT path to i.MX architecture
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-01 18:31 ` [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
2018-02-01 18:31 ` [PATCH v2 3/4] arm64: add support for i.MX8M EVK board Lucas Stach
@ 2018-02-01 18:31 ` Lucas Stach
2 siblings, 0 replies; 31+ messages in thread
From: Lucas Stach @ 2018-02-01 18:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
Shawn agreed to take patches for the i.MX8 parts through his tree.
Also add the NXP Linux team as a reviewer.
Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52fd76..5e1f413d9ae5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1382,6 +1382,7 @@ ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
M: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
M: Sascha Hauer <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
R: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
+R: NXP Linux Team <linux-imx-3arQi8VN3Tc@public.gmane.org>
L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
@@ -1389,6 +1390,7 @@ F: arch/arm/mach-imx/
F: arch/arm/mach-mxs/
F: arch/arm/boot/dts/imx*
F: arch/arm/configs/imx*_defconfig
+F: arch/arm64/boot/dts/freescale/imx*
F: drivers/clk/imx/
F: drivers/soc/imx/
F: include/soc/imx/
--
2.15.1
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-02 8:13 ` Jacky Bai
[not found] ` <HE1PR04MB3113FF72B02D642392D625DF87F90-6LN7OEpIatW7Zxc5AHJ2m89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-02-05 6:09 ` Rob Herring
2018-02-05 15:00 ` Marc Zyngier
2 siblings, 1 reply; 31+ messages in thread
From: Jacky Bai @ 2018-02-02 8:13 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, dl-linux-imx, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A.s. Dong, Baruch Siach
> Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
The cpu sleep states can NOT be supported in community kernel due to hardware limitation.
BR
Jacky Bai
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> v2:
> - move to freescale folder
> - change compatibles to "fsl" vendor prefix
> - remove unnecessary newlines
> - move status property to be the last in all node
> - remove imx21 compatibles from UART nodes
> - document compatible
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++
> 3 files changed, 1038 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd705754..85d1c9ec6fa3 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -75,6 +75,10 @@ i.MX6q generic board
> Required root node properties:
> - compatible = "fsl,imx6q";
>
> +i.MX8MQ generic board
> +Required root node properties:
> + - compatible = "fsl,imx8mq";
> +
> Freescale Vybrid Platform Device Tree Bindings
> ----------------------------------------------
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> new file mode 100644
> index 000000000000..b94b02080a34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> @@ -0,0 +1,623 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + */
> +
> +#ifndef __DTS_IMX8MQ_PINFUNC_H
> +#define __DTS_IMX8MQ_PINFUNC_H
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define
> MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ
> 0x014 0x27C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ
> 0x018 0x280 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF
> 0x01C 0x284 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B
> 0x020 0x288 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B
> 0x024 0x28C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0
> 0x028 0x290 0x000 0x0 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
> 0x028 0x290 0x4C0 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> 0x028 0x290 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
> 0x028 0x290 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL
> 0x028 0x290 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1
> 0x02C 0x294 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT
> 0x02C 0x294 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
> 0x02C 0x294 0x4BC 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
> 0x02C 0x294 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE
> 0x02C 0x294 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2
> 0x030 0x298 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0x030 0x298 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
> 0x030 0x298 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B
> 0x030 0x298 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3
> 0x034 0x29C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
> 0x034 0x29C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
> 0x034 0x29C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
> 0x034 0x29C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE
> 0x034 0x29C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4
> 0x038 0x2A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x038 0x2A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
> 0x038 0x2A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
> 0x038 0x2A0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG
> 0x038 0x2A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5
> 0x03C 0x2A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI
> 0x03C 0x2A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
> 0x03C 0x2A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
> 0x03C 0x2A4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG
> 0x03C 0x2A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
> 0x040 0x2A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC
> 0x040 0x2A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B
> 0x040 0x2A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
> 0x040 0x2A8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG
> 0x040 0x2A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
> 0x044 0x2AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO
> 0x044 0x2AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP
> 0x044 0x2AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
> 0x044 0x2AC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG
> 0x044 0x2AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
> 0x048 0x2B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> 0x048 0x2B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B
> 0x048 0x2B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT
> 0x048 0x2B0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG
> 0x048 0x2B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9
> 0x04C 0x2B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> 0x04C 0x2B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0
> 0x04C 0x2B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP
> 0x04C 0x2B4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG
> 0x04C 0x2B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x050 0x2B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID
> 0x050 0x2B8 0x000 0x1 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED
> 0x050 0x2B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11
> 0x054 0x2BC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID
> 0x054 0x2BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY
> 0x054 0x2BC 0x4BC 0x5 0x1
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0
> 0x054 0x2BC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS
> 0x054 0x2BC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x058 0x2C0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR
> 0x058 0x2C0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1
> 0x058 0x2C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1
> 0x058 0x2C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0
> 0x058 0x2C0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13
> 0x05C 0x2C4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC
> 0x05C 0x2C4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT
> 0x05C 0x2C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2
> 0x05C 0x2C4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1
> 0x05C 0x2C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14
> 0x060 0x2C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR
> 0x060 0x2C8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT
> 0x060 0x2C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
> 0x060 0x2C8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2
> 0x060 0x2C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 0x064 0x2CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC
> 0x064 0x2CC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT
> 0x064 0x2CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
> 0x064 0x2CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB
> 0x064 0x2CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC
> 0x068 0x2D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16
> 0x068 0x2D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO
> 0x06C 0x2D4 0x4C0 0x0 0x1
> +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17
> 0x06C 0x2D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x070 0x2D8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18
> 0x070 0x2D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x074 0x2DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK
> 0x074 0x2DC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19
> 0x074 0x2DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x078 0x2E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20
> 0x078 0x2E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x07C 0x2E4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21
> 0x07C 0x2E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x080 0x2E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22
> 0x080 0x2E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x084 0x2EC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER
> 0x084 0x2EC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23
> 0x084 0x2EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 0x088 0x2F0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24
> 0x088 0x2F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x08C 0x2F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER
> 0x08C 0x2F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25
> 0x08C 0x2F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x090 0x2F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26
> 0x090 0x2F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x094 0x2FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27
> 0x094 0x2FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x098 0x300 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28
> 0x098 0x300 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x09C 0x304 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29
> 0x09C 0x304 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x0A0 0x308 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0
> 0x0A0 0x308 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x0A4 0x30C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1
> 0x0A4 0x30C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x0A8 0x310 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2
> 0x0A8 0x31 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x0AC 0x314 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3
> 0x0AC 0x314 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x0B0 0x318 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4
> 0x0B0 0x318 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x0B4 0x31C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5
> 0x0B4 0x31C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x0B8 0x320 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6
> 0x0B8 0x320 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x0BC 0x324 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7
> 0x0BC 0x324 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x0C0 0x328 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8
> 0x0C0 0x328 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x0C4 0x32C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9
> 0x0C4 0x32C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
> 0x0C8 0x330 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10
> 0x0C8 0x330 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x0CC 0x334 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11
> 0x0CC 0x334 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B
> 0x0D0 0x338 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
> 0x0D0 0x338 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
> 0x0D4 0x33C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13
> 0x0D4 0x33C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0
> 0x0D4 0x33C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0
> 0x0D4 0x33C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
> 0x0D8 0x340 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14
> 0x0D8 0x340 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1
> 0x0D8 0x340 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1
> 0x0D8 0x340 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x0DC 0x344 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15
> 0x0DC 0x344 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2
> 0x0DC 0x344 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2
> 0x0DC 0x344 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x0E0 0x348 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16
> 0x0E0 0x348 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT
> 0x0E0 0x348 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3
> 0x0E0 0x348 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x0E4 0x34C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17
> 0x0E4 0x34C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP
> 0x0E4 0x34C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4
> 0x0E4 0x34C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x0E8 0x350 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18
> 0x0E8 0x350 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET
> 0x0E8 0x350 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B
> 0x0EC 0x354 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x0EC 0x354 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET
> 0x0EC 0x354 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP
> 0x0F0 0x358 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20
> 0x0F0 0x358 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK
> 0x0F0 0x358 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE
> 0x0F4 0x35C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK
> 0x0F4 0x35C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0
> 0x0F4 0x35C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0
> 0x0F4 0x35C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B
> 0x0F8 0x360 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x0F8 0x360 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1
> 0x0F8 0x360 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1
> 0x0F8 0x360 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B
> 0x0FC 0x364 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> 0x0FC 0x364 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2
> 0x0FC 0x364 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2
> 0x0FC 0x364 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B
> 0x100 0x368 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B
> 0x100 0x368 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3
> 0x100 0x368 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3
> 0x100 0x368 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B
> 0x104 0x36C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B
> 0x104 0x36C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4
> 0x104 0x36C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0
> 0x104 0x36C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE
> 0x108 0x370 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK
> 0x108 0x370 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5
> 0x108 0x370 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1
> 0x108 0x370 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00
> 0x10C 0x374 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> 0x10C 0x374 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6
> 0x10C 0x374 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2
> 0x10C 0x374 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01
> 0x110 0x378 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> 0x110 0x378 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7
> 0x110 0x378 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3
> 0x110 0x378 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02
> 0x114 0x37C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> 0x114 0x37C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8
> 0x114 0x37C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4
> 0x114 0x37C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03
> 0x118 0x380 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> 0x118 0x380 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
> 0x118 0x380 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5
> 0x118 0x380 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04
> 0x11C 0x384 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0
> 0x11C 0x384 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10
> 0x11C 0x384 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6
> 0x11C 0x384 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05
> 0x120 0x388 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1
> 0x120 0x388 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
> 0x120 0x388 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7
> 0x120 0x388 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06
> 0x124 0x38C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2
> 0x124 0x38C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12
> 0x124 0x38C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8
> 0x124 0x38C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07
> 0x128 0x390 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3
> 0x128 0x390 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13
> 0x128 0x390 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9
> 0x128 0x390 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS
> 0x12C 0x394 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS
> 0x12C 0x394 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14
> 0x12C 0x394 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10
> 0x12C 0x394 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B
> 0x130 0x398 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS
> 0x130 0x398 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15
> 0x130 0x398 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11
> 0x130 0x398 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B
> 0x134 0x39C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x134 0x39C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12
> 0x134 0x39C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B
> 0x138 0x3A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17
> 0x138 0x3A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13
> 0x138 0x3A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B
> 0x13C 0x3A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18
> 0x13C 0x3A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14
> 0x13C 0x3A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC
> 0x140 0x3A8 0x4E4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0
> 0x140 0x3A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19
> 0x140 0x3A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK
> 0x144 0x3AC 0x4D0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1
> 0x144 0x3AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20
> 0x144 0x3AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> 0x148 0x3B0 0x4D4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2
> 0x148 0x3B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21
> 0x148 0x3B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1
> 0x14C 0x3B4 0x4D8 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3
> 0x14C 0x3B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC
> 0x14C 0x3B4 0x4CC 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> 0x14C 0x3B4 0x4EC 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22
> 0x14C 0x3B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2
> 0x150 0x3B8 0x4DC 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4
> 0x150 0x3B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC
> 0x150 0x3B8 0x4CC 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> 0x150 0x3B8 0x4E8 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23
> 0x150 0x3B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3
> 0x154 0x3BC 0x4E0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5
> 0x154 0x3BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC
> 0x154 0x3BC 0x4CC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> 0x154 0x3BC 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24
> 0x154 0x3BC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK
> 0x158 0x3C0 0x52C 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK
> 0x158 0x3C0 0x4C8 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK
> 0x158 0x3C0 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25
> 0x158 0x3C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK
> 0x158 0x3C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC
> 0x15C 0x3C4 0x4C4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC
> 0x15C 0x3C4 0x4E4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK
> 0x15C 0x3C4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 0x15C 0x3C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15
> 0x15C 0x3C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK
> 0x160 0x3C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK
> 0x160 0x3C8 0x4D0 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL
> 0x160 0x3C8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1
> 0x160 0x3C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16
> 0x160 0x3C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0
> 0x164 0x3CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0
> 0x164 0x3CC 0x4D4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0
> 0x164 0x3CC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2
> 0x164 0x3CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0
> 0x164 0x3CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17
> 0x164 0x3CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1
> 0x168 0x3D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1
> 0x168 0x3D0 0x4D8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1
> 0x168 0x3D0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3
> 0x168 0x3D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1
> 0x168 0x3D0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18
> 0x168 0x3D0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2
> 0x16C 0x3D4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2
> 0x16C 0x3D4 0x4DC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2
> 0x16C 0x3D4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4
> 0x16C 0x3D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2
> 0x16C 0x3D4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19
> 0x16C 0x3D4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3
> 0x170 0x3D8 0x4E0 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3
> 0x170 0x3D8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3
> 0x170 0x3D8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5
> 0x170 0x3D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3
> 0x170 0x3D8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20
> 0x170 0x3D8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4
> 0x174 0x3DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK
> 0x174 0x3DC 0x51C 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK
> 0x174 0x3DC 0x510 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4
> 0x174 0x3DC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6
> 0x174 0x3DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4
> 0x174 0x3DC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21
> 0x174 0x3DC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5
> 0x178 0x3E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0
> 0x178 0x3E0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0
> 0x178 0x3E0 0x514 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC
> 0x178 0x3E0 0x4C4 0x3 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5
> 0x178 0x3E0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7
> 0x178 0x3E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5
> 0x178 0x3E0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22
> 0x178 0x3E0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6
> 0x17C 0x3E4 0x520 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC
> 0x17C 0x3E4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC
> 0x17C 0x3E4 0x518 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6
> 0x17C 0x3E4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8
> 0x17C 0x3E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6
> 0x17C 0x3E4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23
> 0x17C 0x3E4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7
> 0x180 0x3E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK
> 0x180 0x3E8 0x530 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC
> 0x180 0x3E8 0x4CC 0x2 0x4
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4
> 0x180 0x3E8 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7
> 0x180 0x3E8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9
> 0x180 0x3E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7
> 0x180 0x3E8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24
> 0x180 0x3E8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
> 0x184 0x3EC 0x4CC 0x0 0x3
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC
> 0x184 0x3EC 0x4EC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO
> 0x184 0x3EC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10
> 0x184 0x3EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25
> 0x184 0x3EC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
> 0x188 0x3F0 0x4C8 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK
> 0x188 0x3F0 0x4E8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI
> 0x188 0x3F0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11
> 0x188 0x3F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26
> 0x188 0x3F0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
> 0x18C 0x3F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0
> 0x18C 0x3F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8
> 0x18C 0x3F4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12
> 0x18C 0x3F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8
> 0x18C 0x3F4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27
> 0x18C 0x3F4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
> 0x190 0x3F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1
> 0x190 0x3F8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9
> 0x190 0x3F8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13
> 0x190 0x3F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9
> 0x190 0x3F8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28
> 0x190 0x3F8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
> 0x194 0x3FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2
> 0x194 0x3FC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10
> 0x194 0x3FC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14
> 0x194 0x3FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10
> 0x194 0x3FC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29
> 0x194 0x3FC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
> 0x198 0x400 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3
> 0x198 0x400 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11
> 0x198 0x400 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15
> 0x198 0x400 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11
> 0x198 0x400 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30
> 0x198 0x400 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
> 0x19C 0x404 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK
> 0x19C 0x404 0x510 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK
> 0x19C 0x404 0x51C 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12
> 0x19C 0x404 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16
> 0x19C 0x404 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12
> 0x19C 0x404 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31
> 0x19C 0x404 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
> 0x1A0 0x408 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0
> 0x1A0 0x408 0x514 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0
> 0x1A0 0x408 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13
> 0x1A0 0x408 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17
> 0x1A0 0x408 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13
> 0x1A0 0x408 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0
> 0x1A0 0x408 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
> 0x1A4 0x40C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC
> 0x1A4 0x40C 0x518 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC
> 0x1A4 0x40C 0x520 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14
> 0x1A4 0x40C 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18
> 0x1A4 0x40C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14
> 0x1A4 0x40C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1
> 0x1A4 0x40C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
> 0x1A8 0x410 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK
> 0x1A8 0x410 0x530 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15
> 0x1A8 0x410 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19
> 0x1A8 0x410 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15
> 0x1A8 0x410 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2
> 0x1A8 0x410 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK
> 0x1AC 0x414 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK
> 0x1AC 0x414 0x52C 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK
> 0x1AC 0x414 0x4C8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20
> 0x1AC 0x414 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP
> 0x1AC 0x414 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC
> 0x1B0 0x418 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC
> 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21
> 0x1B0 0x418 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0
> 0x1B0 0x418 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK
> 0x1B4 0x41C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK
> 0x1B4 0x41C 0x4E8 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22
> 0x1B4 0x41C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1
> 0x1B4 0x41C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> 0x1B8 0x420 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0
> 0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23
> 0x1B8 0x420 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2
> 0x1B8 0x420 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> 0x1BC 0x424 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1
> 0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24
> 0x1BC 0x424 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE
> 0x1BC 0x424 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> 0x1C0 0x428 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2
> 0x1C0 0x428 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25
> 0x1C0 0x428 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT
> 0x1C0 0x428 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> 0x1C4 0x42C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3
> 0x1C4 0x42C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26
> 0x1C4 0x42C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK
> 0x1C4 0x42C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK
> 0x1C8 0x430 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK
> 0x1C8 0x430 0x52C 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27
> 0x1C8 0x430 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR
> 0x1C8 0x430 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC
> 0x1CC 0x434 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1
> 0x1CC 0x434 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC
> 0x1CC 0x434 0x4E4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28
> 0x1CC 0x434 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0
> 0x1CC 0x434 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> 0x1D0 0x438 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2
> 0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> 0x1D0 0x438 0x4D0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29
> 0x1D0 0x438 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1
> 0x1D0 0x438 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> 0x1D4 0x43C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> 0x1D4 0x43C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> 0x1D4 0x43C 0x4D4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30
> 0x1D4 0x43C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0
> 0x1D4 0x43C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> 0x1D8 0x440 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK
> 0x1D8 0x440 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> 0x1D8 0x440 0x4D8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31
> 0x1D8 0x440 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1
> 0x1D8 0x440 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> 0x1DC 0x444 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> 0x1DC 0x444 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> 0x1DC 0x444 0x4DC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0
> 0x1DC 0x444 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2
> 0x1DC 0x444 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> 0x1E0 0x448 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3
> 0x1E0 0x448 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3
> 0x1E0 0x448 0x4E0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1
> 0x1E0 0x448 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3
> 0x1E0 0x448 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK
> 0x1E4 0x44C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT
> 0x1E4 0x44C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK
> 0x1E4 0x44C 0x52C 0x2 0x3
> +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2
> 0x1E4 0x44C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4
> 0x1E4 0x44C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT
> 0x1E8 0x450 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT
> 0x1E8 0x450 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3
> 0x1E8 0x450 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5
> 0x1E8 0x450 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN
> 0x1EC 0x454 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT
> 0x1EC 0x454 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4
> 0x1EC 0x454 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6
> 0x1EC 0x454 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK
> 0x1F0 0x458 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT
> 0x1F0 0x458 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> 0x1F0 0x458 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7
> 0x1F0 0x458 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
> 0x1F4 0x45C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> 0x1F4 0x45C 0x504 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX
> 0x1F4 0x45C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6
> 0x1F4 0x45C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8
> 0x1F4 0x45C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
> 0x1F8 0x460 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> 0x1F8 0x460 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX
> 0x1F8 0x460 0x504 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7
> 0x1F8 0x460 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9
> 0x1F8 0x460 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
> 0x1FC 0x464 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B
> 0x1FC 0x464 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B
> 0x1FC 0x464 0x500 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> 0x1FC 0x464 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10
> 0x1FC 0x464 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0
> 0x200 0x468 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> 0x200 0x468 0x500 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B
> 0x200 0x468 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9
> 0x200 0x468 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11
> 0x200 0x468 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> 0x204 0x46C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
> 0x204 0x46C 0x50C 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX
> 0x204 0x46C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10
> 0x204 0x46C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12
> 0x204 0x46C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> 0x208 0x470 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
> 0x208 0x470 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX
> 0x208 0x470 0x50C 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11
> 0x208 0x470 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13
> 0x208 0x470 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> 0x20C 0x474 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
> 0x20C 0x474 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B
> 0x20C 0x474 0x508 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12
> 0x20C 0x474 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14
> 0x20C 0x474 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0
> 0x210 0x478 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
> 0x210 0x478 0x508 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B
> 0x210 0x478 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> 0x210 0x478 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15
> 0x210 0x478 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x214 0x47C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC
> 0x214 0x47C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14
> 0x214 0x47C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16
> 0x214 0x47C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x218 0x480 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO
> 0x218 0x480 0x4C0 0x1 0x2
> +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15
> 0x218 0x480 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17
> 0x218 0x480 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL
> 0x21C 0x484 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN
> 0x21C 0x484 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16
> 0x21C 0x484 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18
> 0x21C 0x484 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA
> 0x220 0x488 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT
> 0x220 0x488 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17
> 0x220 0x488 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19
> 0x220 0x488 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL
> 0x224 0x48C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT
> 0x224 0x48C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK
> 0x224 0x48C 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18
> 0x224 0x48C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20
> 0x224 0x48C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA
> 0x228 0x490 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT
> 0x228 0x490 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK
> 0x228 0x490 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19
> 0x228 0x490 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21
> 0x228 0x490 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
> 0x22C 0x494 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT
> 0x22C 0x494 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B
> 0x22C 0x494 0x524 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20
> 0x22C 0x494 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22
> 0x22C 0x494 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
> 0x230 0x498 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT
> 0x230 0x498 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B
> 0x230 0x498 0x528 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21
> 0x230 0x498 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23
> 0x230 0x498 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x234 0x49C 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX
> 0x234 0x49C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK
> 0x234 0x49C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22
> 0x234 0x49C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24
> 0x234 0x49C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x238 0x4A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX
> 0x238 0x4A0 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI
> 0x238 0x4A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23
> 0x238 0x4A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25
> 0x238 0x4A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX
> 0x23C 0x4A4 0x4FC 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX
> 0x23C 0x4A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO
> 0x23C 0x4A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24
> 0x23C 0x4A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26
> 0x23C 0x4A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX
> 0x240 0x4A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX
> 0x240 0x4A8 0x4FC 0x0 0x1
> +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0
> 0x240 0x4A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25
> 0x240 0x4A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27
> 0x240 0x4A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX
> 0x244 0x4AC 0x504 0x0 0x2
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX
> 0x244 0x4AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B
> 0x244 0x4AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B
> 0x244 0x4AC 0x4F0 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26
> 0x244 0x4AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28
> 0x244 0x4AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX
> 0x248 0x4B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX
> 0x248 0x4B0 0x504 0x0 0x3
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B
> 0x248 0x4B0 0x4F0 0x1 0x1
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B
> 0x248 0x4B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27
> 0x248 0x4B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29
> 0x248 0x4B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX
> 0x24C 0x4B4 0x50C 0x0 0x2
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX
> 0x24C 0x4B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
> 0x24C 0x4B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B
> 0x24C 0x4B4 0x4F8 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B
> 0x24C 0x4B4 0x524 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28
> 0x24C 0x4B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30
> 0x24C 0x4B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX
> 0x250 0x4B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX
> 0x250 0x4B8 0x50C 0x0 0x3
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
> 0x250 0x4B8 0x4F8 0x1 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B
> 0x250 0x4B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B
> 0x250 0x4B8 0x528 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29
> 0x250 0x4B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31
> 0x250 0x4B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_TEST_MODE
> 0x000 0x254 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE0
> 0x000 0x258 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE1
> 0x000 0x25C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_MOD
> 0x000 0x260 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TRST_B
> 0x000 0x264 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDI
> 0x000 0x268 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TMS
> 0x000 0x26C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TCK
> 0x000 0x270 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDO
> 0x000 0x274 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC
> 0x000 0x278 0x000 0x0 0x0
> +
> +#endif /* __DTS_IMX8MQ_PINFUNC_H */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010033>;
> + local-timer-stop;
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> + };
> +
> + A53_0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> + clock-frequency = <8333333>;
> + interrupt-parent = <&gic>;
> + arm,no-tick-in-suspend;
> + };
> +
> + peripherals@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> + bus@30000000 { /* AIPS1 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30000000 0x30000000 0x400000>;
> +
> + gpio1: gpio@30200000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@30210000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30210000 0x10000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@30220000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30220000 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@30230000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30230000 0x10000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio@30240000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30240000 0x10000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + iomuxc: iomuxc@30330000 {
> + compatible = "fsl,imx8mq-iomuxc";
> + reg = <0x30330000 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr@30340000 {
> + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
> + reg = <0x30340000 0x10000>;
> + };
> +
> + anatop: anatop@30360000 {
> + compatible = "fsl,imx8mq-anatop", "syscon";
> + reg = <0x30360000 0x10000>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + clk: clock-controller@30380000 {
> + compatible = "fsl,imx8mq-ccm";
> + reg = <0x30380000 0x10000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> + <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "ckil", "osc_25m", "osc_27m",
> + "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> + };
> +
> + bus@30400000 { /* AIPS2 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30400000 0x30400000 0x400000>;
> + };
> +
> + bus@30800000 { /* AIPS3 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30800000 0x30800000 0x400000>;
> +
> + uart1: serial@30860000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> + <&clk IMX8MQ_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial@30880000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> + <&clk IMX8MQ_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial@30890000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> + <&clk IMX8MQ_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@30a20000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a20000 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@30a30000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a30000 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@30a40000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a40000 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@30a50000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a50000 0x10000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + uart4: serial@30a60000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30a60000 0x10000>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> + <&clk IMX8MQ_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: usdhc@30b40000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc@30b50000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet@30be0000 {
> + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> + reg = <0x30be0000 0x10000>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> + <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> + clock-names = "ipg", "ahb", "ptp",
> + "enet_clk_ref", "enet_out";
> + fsl,num-tx-queues = <3>;
> + fsl,num-rx-queues = <3>;
> + status = "disabled";
> + };
> + };
> +
> + gic: interrupt-controller@38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base)
> */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> + };
> +};
> --
> 2.15.1
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-02 8:13 ` Jacky Bai
@ 2018-02-05 6:09 ` Rob Herring
2018-02-05 15:00 ` Marc Zyngier
2 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2018-02-05 6:09 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
On Thu, Feb 01, 2018 at 07:31:24PM +0100, Lucas Stach wrote:
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> v2:
> - move to freescale folder
> - change compatibles to "fsl" vendor prefix
> - remove unnecessary newlines
> - move status property to be the last in all node
> - remove imx21 compatibles from UART nodes
> - document compatible
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++
> 3 files changed, 1038 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
[not found] ` <20180201183126.32384-3-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-05 6:09 ` Rob Herring
2018-02-05 7:24 ` Baruch Siach
1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2018-02-05 6:09 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Mark Rutland, Catalin Marinas, Will Deacon,
Fabio Estevam, NXP Linux Team, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong, Baruch Siach
On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> This is the evaluation kit board for the i.MX8M. The current level of
> support yields a working console and is able to boot userspace from
> SD card or Network.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> (v1)
> Tested-by: Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> (v1)
> ---
> v2:
> - move to freescale folder
> - fix indentation
> - fix typo in Makefile
> - document compatible
> - switch to generic pinconf
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm64/boot/dts/freescale/Makefile | 2 +
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 405 ++++++++++++++++++++++++++
> 3 files changed, 411 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-evk.dts
Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
[not found] ` <20180201183126.32384-3-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-05 6:09 ` Rob Herring
@ 2018-02-05 7:24 ` Baruch Siach
[not found] ` <20180205072438.nxvhlqk54d7firbz-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
1 sibling, 1 reply; 31+ messages in thread
From: Baruch Siach @ 2018-02-05 7:24 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Fabio Estevam, NXP Linux Team,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong
Hi Lucas,
On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> This is the evaluation kit board for the i.MX8M. The current level of
> support yields a working console and is able to boot userspace from
> SD card or Network.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> (v1)
> Tested-by: Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> (v1)
I only tested once.
Tested v2 as well, on top of clk v2 and the pinctrl v2 patches.
Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
Would have been nice to have all these series in a single branch somewhere.
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org - tel: +972.2.679.5364, http://www.tkos.co.il -
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
[not found] ` <HE1PR04MB3113FF72B02D642392D625DF87F90-6LN7OEpIatW7Zxc5AHJ2m89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-02-05 8:45 ` Shawn Guo
2018-02-05 9:07 ` Jacky Bai
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-05 8:45 UTC (permalink / raw)
To: Jacky Bai
Cc: Lucas Stach, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Baruch Siach, Catalin Marinas, Will Deacon,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, Rob Herring, dl-linux-imx,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Fabio Estevam, A.s. Dong,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Fri, Feb 02, 2018 at 08:13:56AM +0000, Jacky Bai wrote:
> > Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
> >
> > This adds the basic DTS for the i.MX8MQ.
> > For now only the following peripherals are supported:
> > - IOMUXC (pin controller)
> > - CCM (clock controller)
> > - GPIO
> > - UART
> > - uSDHC (SD/eMMC controller)
> > - FEC (ethernet controller)
> > - i2c
> >
> > This is enough to get a very basic board support up and running.
> >
> > One known limitation is that the driver for the GPC interrupt
> > controller is still missing, rendering the CPU sleep states unusable
> > as there is nothing waking them up anymore. This will be fixed in
> > due course.
> >
>
> The cpu sleep states can NOT be supported in community kernel due to hardware limitation.
Jacky,
Can you elaborate your comment a bit? If it's a hardware limitation, I
guess not only community but also vendor kernel has no way to support
sleep states, right?
Shawn
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^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-05 8:45 ` Shawn Guo
@ 2018-02-05 9:07 ` Jacky Bai
0 siblings, 0 replies; 31+ messages in thread
From: Jacky Bai @ 2018-02-05 9:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Lucas Stach, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
Baruch Siach, Catalin Marinas, Will Deacon,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, Rob Herring, dl-linux-imx,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Fabio Estevam, A.s. Dong,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
> Subject: Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>
> On Fri, Feb 02, 2018 at 08:13:56AM +0000, Jacky Bai wrote:
> > > Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
> > >
> > > This adds the basic DTS for the i.MX8MQ.
> > > For now only the following peripherals are supported:
> > > - IOMUXC (pin controller)
> > > - CCM (clock controller)
> > > - GPIO
> > > - UART
> > > - uSDHC (SD/eMMC controller)
> > > - FEC (ethernet controller)
> > > - i2c
> > >
> > > This is enough to get a very basic board support up and running.
> > >
> > > One known limitation is that the driver for the GPC interrupt
> > > controller is still missing, rendering the CPU sleep states unusable
> > > as there is nothing waking them up anymore. This will be fixed in
> > > due course.
> > >
> >
> > The cpu sleep states can NOT be supported in community kernel due to
> hardware limitation.
>
> Jacky,
>
> Can you elaborate your comment a bit? If it's a hardware limitation, I guess
> not only community but also vendor kernel has no way to support sleep states,
> right?
>
> Shawn
It need to add a workaround in GIC common code, maybe it can NOT be accepted by community.
BR
Jacky bai
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
[not found] ` <20180205072438.nxvhlqk54d7firbz-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
@ 2018-02-05 11:10 ` Lucas Stach
2018-02-23 3:46 ` Shawn Guo
0 siblings, 1 reply; 31+ messages in thread
From: Lucas Stach @ 2018-02-05 11:10 UTC (permalink / raw)
To: Baruch Siach
Cc: Shawn Guo, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Fabio Estevam, NXP Linux Team,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, A . s . Dong
Hi Baruch,
Am Montag, den 05.02.2018, 09:24 +0200 schrieb Baruch Siach:
> Hi Lucas,
>
> On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > This is the evaluation kit board for the i.MX8M. The current level
> > of
> > support yields a working console and is able to boot userspace from
> > SD card or Network.
> >
> > Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> > Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> (v1)
> > Tested-by: Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> (v1)
>
> I only tested once.
Hehe, seems I was a little tired after reworking all those patches. ;)
>
> Tested v2 as well, on top of clk v2 and the pinctrl v2 patches.
>
> Tested-by: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
Thanks.
> Would have been nice to have all these series in a single branch
> somewhere.
I've pushed a branch with all the MX8M work to:
https://git.pengutronix.de/git/lst/linux mx8-work
I'll update this branch if I need to do another revision of this
patchset.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-02 8:13 ` Jacky Bai
2018-02-05 6:09 ` Rob Herring
@ 2018-02-05 15:00 ` Marc Zyngier
2 siblings, 0 replies; 31+ messages in thread
From: Marc Zyngier @ 2018-02-05 15:00 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Baruch Siach,
Catalin Marinas, Will Deacon,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ, Rob Herring,
NXP Linux Team, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Fabio Estevam,
A . s . Dong, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 01/02/18 18:31, Lucas Stach wrote:
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> v2:
> - move to freescale folder
> - change compatibles to "fsl" vendor prefix
> - remove unnecessary newlines
> - move status property to be the last in all node
> - remove imx21 compatibles from UART nodes
> - document compatible
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++
> 3 files changed, 1038 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
>
[...]
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010033>;
> + local-timer-stop;
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> + };
> +
> + A53_0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
GICv3 doesn't have express PPI affinity this way (and 6 feels slightly
wrong anyway).
> + clock-frequency = <8333333>;
Really? Can't firmware be fixed, and/or the property overridden for
boards that are known to ship with a broken firmware?
> + interrupt-parent = <&gic>;
> + arm,no-tick-in-suspend;
/me very sad.
> + };
> +
> + peripherals@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> + bus@30000000 { /* AIPS1 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30000000 0x30000000 0x400000>;
> +
> + gpio1: gpio@30200000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@30210000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30210000 0x10000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@30220000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30220000 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@30230000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30230000 0x10000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio@30240000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30240000 0x10000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + iomuxc: iomuxc@30330000 {
> + compatible = "fsl,imx8mq-iomuxc";
> + reg = <0x30330000 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr@30340000 {
> + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
> + reg = <0x30340000 0x10000>;
> + };
> +
> + anatop: anatop@30360000 {
> + compatible = "fsl,imx8mq-anatop", "syscon";
> + reg = <0x30360000 0x10000>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + clk: clock-controller@30380000 {
> + compatible = "fsl,imx8mq-ccm";
> + reg = <0x30380000 0x10000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> + <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "ckil", "osc_25m", "osc_27m",
> + "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> + };
> +
> + bus@30400000 { /* AIPS2 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30400000 0x30400000 0x400000>;
> + };
> +
> + bus@30800000 { /* AIPS3 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30800000 0x30800000 0x400000>;
> +
> + uart1: serial@30860000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> + <&clk IMX8MQ_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial@30880000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> + <&clk IMX8MQ_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial@30890000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> + <&clk IMX8MQ_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@30a20000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a20000 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@30a30000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a30000 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@30a40000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a40000 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@30a50000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a50000 0x10000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + uart4: serial@30a60000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30a60000 0x10000>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> + <&clk IMX8MQ_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: usdhc@30b40000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc@30b50000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet@30be0000 {
> + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> + reg = <0x30be0000 0x10000>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> + <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> + clock-names = "ipg", "ahb", "ptp",
> + "enet_clk_ref", "enet_out";
> + fsl,num-tx-queues = <3>;
> + fsl,num-rx-queues = <3>;
> + status = "disabled";
> + };
> + };
> +
> + gic: interrupt-controller@38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
You are missing the memory-mapped version of the CPU interface (GICC,
GICH, GICV), which Cortex-A53 implements (see [1] for details).
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> + };
> +};
>
Thanks,
M.
[1]
http://arminfo.emea.arm.com/help/topic/com.arm.doc.ddi0500g/ch09s02s01.html
--
Jazz is not dead. It just smells funny...
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-05 11:10 ` Lucas Stach
@ 2018-02-23 3:46 ` Shawn Guo
2018-02-23 4:32 ` Baruch Siach
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-23 3:46 UTC (permalink / raw)
To: Lucas Stach
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel
Hi Lucas,
On Mon, Feb 05, 2018 at 12:10:46PM +0100, Lucas Stach wrote:
> I've pushed a branch with all the MX8M work to:
> https://git.pengutronix.de/git/lst/linux mx8-work
I have some problem to boot the kernel (and dtb) built from this branch.
I'm running an U-Boot from NXP which works fine with NXP kernel for
sure. But using this U-Boot to load your kernel gives me nothing on
serial, even if I put 'earlycon=ec_imx6q,0x30860000' on kernel
cmdline. Anything I'm missing here? Thanks.
Shawn
---8<--------------------------
U-Boot 2017.03-00779-g777f3b0e3c60 (Jan 31 2018 - 13:54:54 +0800)
CPU: Freescale i.MX8MQ rev2.0 1500 MHz (running at 1000 MHz)
CPU: Commercial temperature grade (0C to 95C) at 30C
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM: 3 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
BuildInfo:
- ATF 0
- U-Boot 2017.03-00779-g777f3b0e3c60
switch to partitions #0, OK
mmc1 is current device
Net: eth0: ethernet@30be0000
Normal Boot
Hit any key to stop autoboot: 0
u-boot=> tftpboot 0x42000000 Image; tftpboot 0x48000000 imx8mq-evk.dtb;
booti 0x42000000 - 0x48000000
Using ethernet@30be0000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.110
Filename 'Image'.
Load address: 0x42000000
Loading:
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
###########################################
10.1 MiB/s
done
Bytes transferred = 17803776 (10faa00 hex)
Using ethernet@30be0000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.110
Filename 'imx8mq-evk.dtb'.
Load address: 0x48000000
Loading: #
6.2 MiB/s
done
Bytes transferred = 12999 (32c7 hex)
## Flattened Device Tree blob at 48000000
Booting using the fdt blob at 0x48000000
reserving fdt memory region: addr=40000000 size=20000
Using Device Tree in place at 0000000048000000, end 00000000480062c6
Starting kernel ...
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 3:46 ` Shawn Guo
@ 2018-02-23 4:32 ` Baruch Siach
2018-02-23 7:05 ` Shawn Guo
0 siblings, 1 reply; 31+ messages in thread
From: Baruch Siach @ 2018-02-23 4:32 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Catalin Marinas, Will Deacon,
patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel, Lucas Stach
[-- Attachment #1: Type: text/plain, Size: 901 bytes --]
Hi Sawn,
On Fri, Feb 23, 2018 at 11:46:53AM +0800, Shawn Guo wrote:
> On Mon, Feb 05, 2018 at 12:10:46PM +0100, Lucas Stach wrote:
> > I've pushed a branch with all the MX8M work to:
> > https://git.pengutronix.de/git/lst/linux mx8-work
>
> I have some problem to boot the kernel (and dtb) built from this branch.
> I'm running an U-Boot from NXP which works fine with NXP kernel for
> sure. But using this U-Boot to load your kernel gives me nothing on
> serial, even if I put 'earlycon=ec_imx6q,0x30860000' on kernel
> cmdline. Anything I'm missing here? Thanks.
FWIW, I tested these patches on the i.MX8 EVK with the attached defconfig.
Hope this helps,
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
[-- Attachment #2: imx8_evk_defconfig --]
[-- Type: text/plain, Size: 7379 bytes --]
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_CPU_ISOLATION is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_JUMP_LABEL=y
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_MXC=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
CONFIG_PREEMPT=y
CONFIG_KSM=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_CMA=y
# CONFIG_ARM64_SVE is not set
# CONFIG_EFI is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
CONFIG_HIBERNATION=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_CPU_FREQ=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_MANGLE=y
CONFIG_DNS_RESOLVER=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_VEXPRESS_CONFIG=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_VEXPRESS_SYSCFG is not set
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_LIBSAS=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_EXAR is not set
CONFIG_FEC=y
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_NET_PACKET_ENGINE is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
CONFIG_AT803X_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_MISC=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_AMBAKMI=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_HW_RANDOM_CAVIUM is not set
# CONFIG_DEVPORT is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_SPIDEV=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8MQ=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_THERMAL=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_VEXPRESS_SYSREG is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PFUZE100=y
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
# CONFIG_USB_PCI is not set
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
# CONFIG_COMMON_CLK_XGENE is not set
CONFIG_ARM_TIMER_SP804=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_SOC_IMX8MQ=y
CONFIG_PWM=y
CONFIG_PWM_IMX=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_ARM_PMU is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_FANOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_MEMTEST=y
CONFIG_KEYS=y
# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_HW is not set
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRC32_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 4:32 ` Baruch Siach
@ 2018-02-23 7:05 ` Shawn Guo
0 siblings, 0 replies; 31+ messages in thread
From: Shawn Guo @ 2018-02-23 7:05 UTC (permalink / raw)
To: Baruch Siach
Cc: Mark Rutland, devicetree, Catalin Marinas, Will Deacon,
patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel, Lucas Stach
Hi Baruch,
On Fri, Feb 23, 2018 at 06:32:42AM +0200, Baruch Siach wrote:
> Hi Sawn,
>
> On Fri, Feb 23, 2018 at 11:46:53AM +0800, Shawn Guo wrote:
> > On Mon, Feb 05, 2018 at 12:10:46PM +0100, Lucas Stach wrote:
> > > I've pushed a branch with all the MX8M work to:
> > > https://git.pengutronix.de/git/lst/linux mx8-work
> >
> > I have some problem to boot the kernel (and dtb) built from this branch.
> > I'm running an U-Boot from NXP which works fine with NXP kernel for
> > sure. But using this U-Boot to load your kernel gives me nothing on
> > serial, even if I put 'earlycon=ec_imx6q,0x30860000' on kernel
> > cmdline. Anything I'm missing here? Thanks.
>
> FWIW, I tested these patches on the i.MX8 EVK with the attached defconfig.
>
> Hope this helps,
Yeah, it helps a lot. I forgot the fact that arm64 defconfig file does
not include any i.MX platform options. The serial driver is not even
enabled.
I enabled a few more options on top of your defconfig, and now am able
to boot into the Debian prompt over NFS.
Thanks for help.
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8
2018-02-01 18:31 [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8 Lucas Stach
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-23 14:56 ` Shawn Guo
2018-02-25 10:17 ` A.s. Dong
1 sibling, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-23 14:56 UTC (permalink / raw)
To: Lucas Stach
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel
On Thu, Feb 01, 2018 at 07:31:23PM +0100, Lucas Stach wrote:
> Add basic Kconfig symbols to make the MXC architecture available
> in the ARM64 world.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
> v2: fix "enabled" typo.
> ---
> arch/arm64/Kconfig.platforms | 6 ++++++
> drivers/soc/imx/Kconfig | 12 ++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 2401373565ff..ae3be0d2cdb5 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -131,6 +131,12 @@ config ARCH_MVEBU
> - Armada 7K SoC Family
> - Armada 8K SoC Family
>
> +config ARCH_MXC
> + bool "ARMv8 based NXP i.MX SoC family"
> + help
> + This enables support for the ARMv8 based SoCs in the
> + NXP i.MX family.
> +
> config ARCH_QCOM
> bool "Qualcomm Platforms"
> select GPIOLIB
> diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
> index a5b86a28f343..8c9f04440896 100644
> --- a/drivers/soc/imx/Kconfig
> +++ b/drivers/soc/imx/Kconfig
> @@ -8,3 +8,15 @@ config IMX7_PM_DOMAINS
> default y if SOC_IMX7D
>
> endmenu
> +
> +if ARCH_MXC
> +
> +if ARM64
> +
> +config SOC_IMX8MQ
> + bool "i.MX8MQ support"
> + help
> + This enables support for the i.MX8MQ SoC.
> +endif
> +
> +endif
I do not feel it's so idiomatic to select a platform SoC in drivers/soc
folder. The options in this folder are used to select SoC level drivers
not the SoC itself. Can we just use ARCH_MXC for all IMX ARMv8 SoCs?
Or if we really want individual SoC option, can we do something similar
to Renesas platform, having sub-select under "ARMv8 based NXP i.MX SoC
family"?
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-01 18:31 ` [PATCH v2 3/4] arm64: add support for i.MX8M EVK board Lucas Stach
[not found] ` <20180201183126.32384-3-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-23 15:03 ` Shawn Guo
2018-02-23 15:30 ` Juergen Borleis
2018-02-23 15:45 ` Lucas Stach
1 sibling, 2 replies; 31+ messages in thread
From: Shawn Guo @ 2018-02-23 15:03 UTC (permalink / raw)
To: Lucas Stach
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel
On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
> + <&pinctrl_usdhc1_data>;
> + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> + <&pinctrl_usdhc1_data_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> + <&pinctrl_usdhc1_data_200mhz>;
> + vqmmc-supply = <&sw4_reg>;
> + bus-width = <8>;
> + non-removable;
> + no-sd;
> + no-sdio;
> + status = "okay";
> +};
I'm not sure it can be enabled right now. Per my testing, eMMC is not
working yet.
[ 0.879756] mmc0: Switching to 3.3V signalling voltage failed
[ 0.913587] mmc0: SDHCI controller on 30b40000.usdhc [30b40000.usdhc] using ADMA
...
[ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-110
[ 1.013873] mmc0: error -110 whilst initialising MMC card
[ 1.020639] mmc0: Switching to 3.3V signalling voltage failed
...
[ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-110
[ 1.138674] mmc0: error -110 whilst initialising MMC card
[ 1.145394] mmc0: Switching to 3.3V signalling voltage failed
[ 1.268367] mmc0: switch to high-speed from hs200 failed, err:-110
[ 1.274576] mmc0: error -110 whilst initialising MMC card
[ 1.281291] mmc0: Switching to 3.3V signalling voltage failed
[ 1.440708] mmc0: switch to high-speed from hs200 failed, err:-110
[ 1.446919] mmc0: error -110 whilst initialising MMC card
Or am I missing anything?
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 15:03 ` Shawn Guo
@ 2018-02-23 15:30 ` Juergen Borleis
2018-02-23 15:46 ` Lucas Stach
2018-02-23 15:45 ` Lucas Stach
1 sibling, 1 reply; 31+ messages in thread
From: Juergen Borleis @ 2018-02-23 15:30 UTC (permalink / raw)
To: kernel
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team,
Fabio Estevam, Shawn Guo, A . s . Dong, linux-arm-kernel,
Lucas Stach
On Friday 23 February 2018 16:03:53 Shawn Guo wrote:
> On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > +&usdhc1 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
> > + <&pinctrl_usdhc1_data>;
> > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> > + <&pinctrl_usdhc1_data_100mhz>;
> > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> > + <&pinctrl_usdhc1_data_200mhz>;
> > + vqmmc-supply = <&sw4_reg>;
> > + bus-width = <8>;
> > + non-removable;
> > + no-sd;
> > + no-sdio;
> > + status = "okay";
> > +};
>
> I'm not sure it can be enabled right now. Per my testing, eMMC is not
> working yet.
>
> [ 0.879756] mmc0: Switching to 3.3V signalling voltage failed
> [ 0.913587] mmc0: SDHCI controller on 30b40000.usdhc [30b40000.usdhc]
> using ADMA ...
> [ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.013873] mmc0: error -110 whilst initialising MMC card
> [ 1.020639] mmc0: Switching to 3.3V signalling voltage failed
> ...
> [ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.138674] mmc0: error -110 whilst initialising MMC card
> [ 1.145394] mmc0: Switching to 3.3V signalling voltage failed
> [ 1.268367] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.274576] mmc0: error -110 whilst initialising MMC card
> [ 1.281291] mmc0: Switching to 3.3V signalling voltage failed
> [ 1.440708] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.446919] mmc0: error -110 whilst initialising MMC card
>
> Or am I missing anything?
Property "no-1-8-v;" if no 1.8 V is available?
jb
--
Pengutronix e.K. | Juergen Borleis |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 15:03 ` Shawn Guo
2018-02-23 15:30 ` Juergen Borleis
@ 2018-02-23 15:45 ` Lucas Stach
2018-02-25 10:00 ` A.s. Dong
1 sibling, 1 reply; 31+ messages in thread
From: Lucas Stach @ 2018-02-23 15:45 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel
Am Freitag, den 23.02.2018, 23:03 +0800 schrieb Shawn Guo:
> On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > +&usdhc1 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
> > <&pinctrl_usdhc1_clk_strobe>,
> > + <&pinctrl_usdhc1_data>;
> > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> > + <&pinctrl_usdhc1_data_100mhz>;
> > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> > + <&pinctrl_usdhc1_data_200mhz>;
> > + vqmmc-supply = <&sw4_reg>;
> > + bus-width = <8>;
> > + non-removable;
> > + no-sd;
> > + no-sdio;
> > + status = "okay";
> > +};
>
> I'm not sure it can be enabled right now. Per my testing, eMMC is
> not
> working yet.
>
> [ 0.879756] mmc0: Switching to 3.3V signalling voltage failed
> [ 0.913587] mmc0: SDHCI controller on 30b40000.usdhc
> [30b40000.usdhc] using ADMA
> ...
> [ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.013873] mmc0: error -110 whilst initialising MMC card
> [ 1.020639] mmc0: Switching to 3.3V signalling voltage failed
> ...
> [ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.138674] mmc0: error -110 whilst initialising MMC card
> [ 1.145394] mmc0: Switching to 3.3V signalling voltage failed
> [ 1.268367] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.274576] mmc0: error -110 whilst initialising MMC card
> [ 1.281291] mmc0: Switching to 3.3V signalling voltage failed
> [ 1.440708] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 1.446919] mmc0: error -110 whilst initialising MMC card
>
> Or am I missing anything?
This is something I need to look into. The HS200 switching sequence
seems to try to switch to 3.3V HS mode intermediately, which doesn't
work. Despite the error messages eMMC works fine in my testing.
Regards,
Lucas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 15:30 ` Juergen Borleis
@ 2018-02-23 15:46 ` Lucas Stach
2018-02-24 2:58 ` Bough Chen
0 siblings, 1 reply; 31+ messages in thread
From: Lucas Stach @ 2018-02-23 15:46 UTC (permalink / raw)
To: Juergen Borleis, kernel
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team,
Fabio Estevam, Shawn Guo, A . s . Dong, linux-arm-kernel
Am Freitag, den 23.02.2018, 16:30 +0100 schrieb Juergen Borleis:
> On Friday 23 February 2018 16:03:53 Shawn Guo wrote:
> > On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > > +&usdhc1 {
> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
> <&pinctrl_usdhc1_clk_strobe>,
> > > + <&pinctrl_usdhc1_data>;
> > > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> > > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> > > + <&pinctrl_usdhc1_data_100mhz>;
> > > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> > > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> > > + <&pinctrl_usdhc1_data_200mhz>;
> > > + vqmmc-supply = <&sw4_reg>;
> > > + bus-width = <8>;
> > > + non-removable;
> > > + no-sd;
> > > + no-sdio;
> > > + status = "okay";
> > > +};
> >
> > I'm not sure it can be enabled right now. Per my testing, eMMC is
> not
> > working yet.
> >
> > [ 0.879756] mmc0: Switching to 3.3V signalling voltage failed
> > [ 0.913587] mmc0: SDHCI controller on 30b40000.usdhc
> [30b40000.usdhc]
> > using ADMA ...
> > [ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-
> 110
> > [ 1.013873] mmc0: error -110 whilst initialising MMC card
> > [ 1.020639] mmc0: Switching to 3.3V signalling voltage failed
> > ...
> > [ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-
> 110
> > [ 1.138674] mmc0: error -110 whilst initialising MMC card
> > [ 1.145394] mmc0: Switching to 3.3V signalling voltage failed
> > [ 1.268367] mmc0: switch to high-speed from hs200 failed, err:-
> 110
> > [ 1.274576] mmc0: error -110 whilst initialising MMC card
> > [ 1.281291] mmc0: Switching to 3.3V signalling voltage failed
> > [ 1.440708] mmc0: switch to high-speed from hs200 failed, err:-
> 110
> > [ 1.446919] mmc0: error -110 whilst initialising MMC card
> >
> > Or am I missing anything?
>
> Property "no-1-8-v;" if no 1.8 V is available?
The issue is the other way around: the eMMC is hardwired to 1.8V IO
voltage (which is fine per eMMC spec), so it can't switch to 3.3V mode.
Regards,
Lucas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 15:46 ` Lucas Stach
@ 2018-02-24 2:58 ` Bough Chen
2018-02-24 6:00 ` Shawn Guo
0 siblings, 1 reply; 31+ messages in thread
From: Bough Chen @ 2018-02-24 2:58 UTC (permalink / raw)
To: Lucas Stach, Juergen Borleis, kernel
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx,
Fabio Estevam, Shawn Guo, A.s. Dong, linux-arm-kernel
>-----Original Message-----
>From: Lucas Stach [mailto:l.stach@pengutronix.de]
>Sent: 2018年2月23日 23:46
>To: Juergen Borleis <jbe@pengutronix.de>; kernel@pengutronix.de
>Cc: Shawn Guo <shawnguo@kernel.org>; Mark Rutland
><mark.rutland@arm.com>; devicetree@vger.kernel.org; Baruch Siach
><baruch@tkos.co.il>; Catalin Marinas <catalin.marinas@arm.com>; Will
>Deacon <will.deacon@arm.com>; patchwork-lst@pengutronix.de; Rob Herring
><robh+dt@kernel.org>; dl-linux-imx <linux-imx@nxp.com>; Fabio Estevam
><fabio.estevam@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
>linux-arm-kernel@lists.infradead.org
>Subject: Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
>
>Am Freitag, den 23.02.2018, 16:30 +0100 schrieb Juergen Borleis:
>> On Friday 23 February 2018 16:03:53 Shawn Guo wrote:
>> > On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
>> > > +&usdhc1 {
>> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> > > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
>> <&pinctrl_usdhc1_clk_strobe>,
>> > > + <&pinctrl_usdhc1_data>;
>> > > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
>> > > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
>> > > + <&pinctrl_usdhc1_data_100mhz>;
>> > > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
>> > > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
>> > > + <&pinctrl_usdhc1_data_200mhz>;
>> > > + vqmmc-supply = <&sw4_reg>;
>> > > + bus-width = <8>;
>> > > + non-removable;
>> > > + no-sd;
>> > > + no-sdio;
>> > > + status = "okay";
>> > > +};
>> >
EMMC do not need cd pin, and I notice that pinctrl_usdhc1_cd_reset also contains a usdhc2 pad, this is wrong. So please remove pinctrl_usdhc1_cd_reset.
EMMC I/O voltage is fixed to 1.8v so I think no need to add vqmmc-supply, can remove this property here.
For pinctrl_usdhc1_clk_strobe, clock pad need to be pull down, otherwise you will meet data crc error in hs400 mode.
Best Regards,
Bough Chen
>> > I'm not sure it can be enabled right now. Per my testing, eMMC is
>> not
>> > working yet.
>> >
>> > [ 0.879756] mmc0: Switching to 3.3V signalling voltage failed [
>> > 0.913587] mmc0: SDHCI controller on 30b40000.usdhc
>> [30b40000.usdhc]
>> > using ADMA ...
>> > [ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-
>> 110
>> > [ 1.013873] mmc0: error -110 whilst initialising MMC card [
>> > 1.020639] mmc0: Switching to 3.3V signalling voltage failed ...
>> > [ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-
>> 110
>> > [ 1.138674] mmc0: error -110 whilst initialising MMC card [
>> > 1.145394] mmc0: Switching to 3.3V signalling voltage failed [
>> > 1.268367] mmc0: switch to high-speed from hs200 failed, err:-
>> 110
>> > [ 1.274576] mmc0: error -110 whilst initialising MMC card [
>> > 1.281291] mmc0: Switching to 3.3V signalling voltage failed [
>> > 1.440708] mmc0: switch to high-speed from hs200 failed, err:-
>> 110
>> > [ 1.446919] mmc0: error -110 whilst initialising MMC card
>> >
>> > Or am I missing anything?
>>
>> Property "no-1-8-v;" if no 1.8 V is available?
>
>The issue is the other way around: the eMMC is hardwired to 1.8V IO voltage
>(which is fine per eMMC spec), so it can't switch to 3.3V mode.
>
>Regards,
>Lucas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-24 2:58 ` Bough Chen
@ 2018-02-24 6:00 ` Shawn Guo
2018-02-25 9:54 ` A.s. Dong
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-24 6:00 UTC (permalink / raw)
To: Bough Chen
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, Rob Herring, patchwork-lst, dl-linux-imx, kernel,
Fabio Estevam, A.s. Dong, linux-arm-kernel, Lucas Stach
Hi Bough,
On Sat, Feb 24, 2018 at 02:58:31AM +0000, Bough Chen wrote:
> >Am Freitag, den 23.02.2018, 16:30 +0100 schrieb Juergen Borleis:
> >> On Friday 23 February 2018 16:03:53 Shawn Guo wrote:
> >> > On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> >> > > +&usdhc1 {
> >> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> >> > > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
> >> <&pinctrl_usdhc1_clk_strobe>,
> >> > > + <&pinctrl_usdhc1_data>;
> >> > > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> >> > > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> >> > > + <&pinctrl_usdhc1_data_100mhz>;
> >> > > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> >> > > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> >> > > + <&pinctrl_usdhc1_data_200mhz>;
> >> > > + vqmmc-supply = <&sw4_reg>;
> >> > > + bus-width = <8>;
> >> > > + non-removable;
> >> > > + no-sd;
> >> > > + no-sdio;
> >> > > + status = "okay";
> >> > > +};
> >> >
>
> EMMC do not need cd pin, and I notice that pinctrl_usdhc1_cd_reset also contains a usdhc2 pad, this is wrong. So please remove pinctrl_usdhc1_cd_reset.
> EMMC I/O voltage is fixed to 1.8v so I think no need to add vqmmc-supply, can remove this property here.
> For pinctrl_usdhc1_clk_strobe, clock pad need to be pull down, otherwise you will meet data crc error in hs400 mode.
Thanks for the input. I suspect that there are more than what you
suggest here. I remove vqmmc-supply and use the exactly same
pinctrl_usdhc1 as NXP kernel, but still see errors below.
[ 0.952795] mmc0: SDHCI controller on 30b40000.usdhc [30b40000.usdhc] using ADMA
[ 1.054622] mmc0: Tuning failed, falling back to fixed sampling clock
[ 1.076458] mmc0: new HS400 MMC card at address 0001
[ 1.081980] mmcblk0: mmc0:0001 R1J56L 13.8 GiB
[ 1.086880] mmcblk0boot0: mmc0:0001 R1J56L partition 1 4.00 MiB
[ 1.093156] mmcblk0boot1: mmc0:0001 R1J56L partition 2 4.00 MiB
[ 1.099220] mmcblk0rpmb: mmc0:0001 R1J56L partition 3 128 KiB, chardev (248:0)
[ 1.148214] mmc0: Tuning failed, falling back to fixed sampling clock
[ 1.266704] print_req_error: I/O error, dev mmcblk0, sector 0
[ 1.273487] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[ 1.358863] print_req_error: I/O error, dev mmcblk0, sector 0
[ 1.365640] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[ 1.372816] mmcblk0: unable to read partition table
[ 7.231120] mmc0: switch to high-speed from hs200 failed, err:-110
[ 7.372241] mmc0: switch to high-speed from hs200 failed, err:-110
[ 7.378843] print_req_error: I/O error, dev mmcblk0, sector 0
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-24 6:00 ` Shawn Guo
@ 2018-02-25 9:54 ` A.s. Dong
0 siblings, 0 replies; 31+ messages in thread
From: A.s. Dong @ 2018-02-25 9:54 UTC (permalink / raw)
To: Shawn Guo, Bough Chen
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, Rob Herring, patchwork-lst, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel, Lucas Stach
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Saturday, February 24, 2018 2:01 PM
> To: Bough Chen <haibo.chen@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>; Juergen Borleis
> <jbe@pengutronix.de>; kernel@pengutronix.de; Mark Rutland
> <mark.rutland@arm.com>; devicetree@vger.kernel.org; Baruch Siach
> <baruch@tkos.co.il>; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; patchwork-lst@pengutronix.de; Rob
> Herring <robh+dt@kernel.org>; dl-linux-imx <linux-imx@nxp.com>; Fabio
> Estevam <fabio.estevam@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
>
> Hi Bough,
>
> On Sat, Feb 24, 2018 at 02:58:31AM +0000, Bough Chen wrote:
> > >Am Freitag, den 23.02.2018, 16:30 +0100 schrieb Juergen Borleis:
> > >> On Friday 23 February 2018 16:03:53 Shawn Guo wrote:
> > >> > On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > >> > > +&usdhc1 {
> > >> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > >> > > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
> > >> <&pinctrl_usdhc1_clk_strobe>,
> > >> > > + <&pinctrl_usdhc1_data>;
> > >> > > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> > >> > > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> > >> > > + <&pinctrl_usdhc1_data_100mhz>;
> > >> > > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> > >> > > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> > >> > > + <&pinctrl_usdhc1_data_200mhz>;
> > >> > > + vqmmc-supply = <&sw4_reg>;
> > >> > > + bus-width = <8>;
> > >> > > + non-removable;
> > >> > > + no-sd;
> > >> > > + no-sdio;
> > >> > > + status = "okay";
> > >> > > +};
> > >> >
> >
> > EMMC do not need cd pin, and I notice that pinctrl_usdhc1_cd_reset also
> contains a usdhc2 pad, this is wrong. So please remove
> pinctrl_usdhc1_cd_reset.
> > EMMC I/O voltage is fixed to 1.8v so I think no need to add vqmmc-supply,
> can remove this property here.
> > For pinctrl_usdhc1_clk_strobe, clock pad need to be pull down, otherwise
> you will meet data crc error in hs400 mode.
>
> Thanks for the input. I suspect that there are more than what you suggest
> here. I remove vqmmc-supply and use the exactly same
> pinctrl_usdhc1 as NXP kernel, but still see errors below.
>
> [ 0.952795] mmc0: SDHCI controller on 30b40000.usdhc [30b40000.usdhc]
> using ADMA
> [ 1.054622] mmc0: Tuning failed, falling back to fixed sampling clock
> [ 1.076458] mmc0: new HS400 MMC card at address 0001
> [ 1.081980] mmcblk0: mmc0:0001 R1J56L 13.8 GiB
> [ 1.086880] mmcblk0boot0: mmc0:0001 R1J56L partition 1 4.00 MiB
> [ 1.093156] mmcblk0boot1: mmc0:0001 R1J56L partition 2 4.00 MiB
> [ 1.099220] mmcblk0rpmb: mmc0:0001 R1J56L partition 3 128 KiB, chardev
> (248:0)
> [ 1.148214] mmc0: Tuning failed, falling back to fixed sampling clock
> [ 1.266704] print_req_error: I/O error, dev mmcblk0, sector 0
> [ 1.273487] Buffer I/O error on dev mmcblk0, logical block 0, async page
> read
> [ 1.358863] print_req_error: I/O error, dev mmcblk0, sector 0
> [ 1.365640] Buffer I/O error on dev mmcblk0, logical block 0, async page
> read
> [ 1.372816] mmcblk0: unable to read partition table
> [ 7.231120] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 7.372241] mmc0: switch to high-speed from hs200 failed, err:-110
> [ 7.378843] print_req_error: I/O error, dev mmcblk0, sector 0
>
I did a few debug and made it work with below changes.
There's a few quirk delays used in downstream tree to handle some special
characteristic for uSDHC tuning.
Haibo is uSDHC expert from NXP. He can help follow up it later.
I'd suggest not enable HS400 or HS200 in this bring up series at this time
If we can't find a quick and reasonable way to fix it.
>From 0520477f5020632abdaccde440f0efcf6d284025 Mon Sep 17 00:00:00 2001
From: Dong Aisheng <aisheng.dong@nxp.com>
Date: Sun, 25 Feb 2018 12:23:27 +0800
Subject: [PATCH 1/1] hs400 work new
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 3 ++-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++
drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
drivers/mmc/host/sdhci.c | 5 ++++-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index c0e5ee5d..5da40bd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -167,7 +167,7 @@
<&pinctrl_usdhc2_data_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
+ status = "disabled";
};
&iomuxc {
@@ -316,6 +316,7 @@
>;
drive-strength = <7>;
slew-rate = <3>;
+ input-schmitt-enable;
};
pinctrl_usdhc1_data_200mhz: usdhc1data200grp {
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 50ed302..34fef6c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -357,6 +357,8 @@
clocks = <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+ assigned-clock-rates = <400000000>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8b941f8..d26d3710 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1311,6 +1311,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
sdhci_esdhc_ops.platform_execute_tuning =
esdhc_executing_tuning;
+ host->tuning_delay = 1;
if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e9290a3..548837d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2116,8 +2116,11 @@ static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
- if (ctrl & SDHCI_CTRL_TUNED_CLK)
+ if (ctrl & SDHCI_CTRL_TUNED_CLK) {
+ printk("tuning pass, delay 1ms\n");
+ mdelay(1);
return; /* Success! */
+ }
break;
}
--
2.7.4
Regards
Dong Aisheng
> Shawn
^ permalink raw reply related [flat|nested] 31+ messages in thread
* RE: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
2018-02-23 15:45 ` Lucas Stach
@ 2018-02-25 10:00 ` A.s. Dong
0 siblings, 0 replies; 31+ messages in thread
From: A.s. Dong @ 2018-02-25 10:00 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
> -----Original Message-----
> From: Lucas Stach [mailto:l.stach@pengutronix.de]
> Sent: Friday, February 23, 2018 11:45 PM
> To: Shawn Guo <shawnguo@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; kernel@pengutronix.de; patchwork-
> lst@pengutronix.de; A.s. Dong <aisheng.dong@nxp.com>; Baruch Siach
> <baruch@tkos.co.il>
> Subject: Re: [PATCH v2 3/4] arm64: add support for i.MX8M EVK board
>
> Am Freitag, den 23.02.2018, 23:03 +0800 schrieb Shawn Guo:
> > On Thu, Feb 01, 2018 at 07:31:25PM +0100, Lucas Stach wrote:
> > > +&usdhc1 {
> > > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > > + pinctrl-0 = <&pinctrl_usdhc1_cd_reset>,
> > > <&pinctrl_usdhc1_clk_strobe>,
> > > + <&pinctrl_usdhc1_data>;
> > > + pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
> > > + <&pinctrl_usdhc1_clk_strobe_100mhz>,
> > > + <&pinctrl_usdhc1_data_100mhz>;
> > > + pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
> > > + <&pinctrl_usdhc1_clk_strobe_200mhz>,
> > > + <&pinctrl_usdhc1_data_200mhz>;
> > > + vqmmc-supply = <&sw4_reg>;
> > > + bus-width = <8>;
> > > + non-removable;
> > > + no-sd;
> > > + no-sdio;
> > > + status = "okay";
> > > +};
> >
> > I'm not sure it can be enabled right now. Per my testing, eMMC is not
> > working yet.
> >
> > [ 0.879756] mmc0: Switching to 3.3V signalling voltage failed [
> > 0.913587] mmc0: SDHCI controller on 30b40000.usdhc [30b40000.usdhc]
> > using ADMA ...
> > [ 1.007628] mmc0: switch to high-speed from hs200 failed, err:-110
> > [ 1.013873] mmc0: error -110 whilst initialising MMC card [
> > 1.020639] mmc0: Switching to 3.3V signalling voltage failed ...
> > [ 1.132462] mmc0: switch to high-speed from hs200 failed, err:-110
> > [ 1.138674] mmc0: error -110 whilst initialising MMC card [
> > 1.145394] mmc0: Switching to 3.3V signalling voltage failed [
> > 1.268367] mmc0: switch to high-speed from hs200 failed, err:-110 [
> > 1.274576] mmc0: error -110 whilst initialising MMC card [ 1.281291]
> > mmc0: Switching to 3.3V signalling voltage failed [ 1.440708] mmc0:
> > switch to high-speed from hs200 failed, err:-110 [ 1.446919] mmc0:
> > error -110 whilst initialising MMC card
> >
> > Or am I missing anything?
>
> This is something I need to look into. The HS200 switching sequence seems to
> try to switch to 3.3V HS mode intermediately, which doesn't work.
The switching to 3.3v seems to happen in mmc_power_up.
As mx8mq evk board eMMC is fixed to 1.8V, I guess this probably will not
cause any real issue rather than a WARNING.
> Despite
> the error messages eMMC works fine in my testing.
It's strange that It did not work at Shawn's and my side.
Regards
Dong Aisheng
>
> Regards,
> Lucas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8
2018-02-23 14:56 ` [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8 Shawn Guo
@ 2018-02-25 10:17 ` A.s. Dong
0 siblings, 0 replies; 31+ messages in thread
From: A.s. Dong @ 2018-02-25 10:17 UTC (permalink / raw)
To: Shawn Guo, Lucas Stach
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Friday, February 23, 2018 10:56 PM
> To: Lucas Stach <l.stach@pengutronix.de>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; kernel@pengutronix.de; patchwork-
> lst@pengutronix.de; A.s. Dong <aisheng.dong@nxp.com>; Baruch Siach
> <baruch@tkos.co.il>
> Subject: Re: [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8
>
> On Thu, Feb 01, 2018 at 07:31:23PM +0100, Lucas Stach wrote:
> > Add basic Kconfig symbols to make the MXC architecture available in
> > the ARM64 world.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
> > ---
> > v2: fix "enabled" typo.
> > ---
> > arch/arm64/Kconfig.platforms | 6 ++++++
> > drivers/soc/imx/Kconfig | 12 ++++++++++++
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/arch/arm64/Kconfig.platforms
> > b/arch/arm64/Kconfig.platforms index 2401373565ff..ae3be0d2cdb5
> 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -131,6 +131,12 @@ config ARCH_MVEBU
> > - Armada 7K SoC Family
> > - Armada 8K SoC Family
> >
> > +config ARCH_MXC
> > + bool "ARMv8 based NXP i.MX SoC family"
> > + help
> > + This enables support for the ARMv8 based SoCs in the
> > + NXP i.MX family.
We select nothing here?
> > +
> > config ARCH_QCOM
> > bool "Qualcomm Platforms"
> > select GPIOLIB
> > diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index
> > a5b86a28f343..8c9f04440896 100644
> > --- a/drivers/soc/imx/Kconfig
> > +++ b/drivers/soc/imx/Kconfig
> > @@ -8,3 +8,15 @@ config IMX7_PM_DOMAINS
> > default y if SOC_IMX7D
> >
> > endmenu
> > +
> > +if ARCH_MXC
> > +
> > +if ARM64
> > +
> > +config SOC_IMX8MQ
> > + bool "i.MX8MQ support"
> > + help
> > + This enables support for the i.MX8MQ SoC.
> > +endif
> > +
> > +endif
>
> I do not feel it's so idiomatic to select a platform SoC in drivers/soc folder.
> The options in this folder are used to select SoC level drivers not the SoC
> itself. Can we just use ARCH_MXC for all IMX ARMv8 SoCs?
> Or if we really want individual SoC option, can we do something similar to
> Renesas platform, having sub-select under "ARMv8 based NXP i.MX SoC
> family"?
>
+1
It looks a bit weird to enable a SoC under drivers/soc.
Currently we still can't see a requirement to support individual SoC option,
So probably, just like other SoC Vendor does, use ARCH_MXC for all IMX V8
SoCs.
Regards
Dong Aisheng
> Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-01 18:31 ` [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
@ 2018-02-25 10:47 ` A.s. Dong
2018-02-26 3:17 ` Shawn Guo
2018-03-09 3:23 ` Shawn Guo
2 siblings, 1 reply; 31+ messages in thread
From: A.s. Dong @ 2018-02-25 10:47 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel
> -----Original Message-----
> From: Lucas Stach [mailto:l.stach@pengutronix.de]
> Sent: Friday, February 2, 2018 2:31 AM
> To: Shawn Guo <shawnguo@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; kernel@pengutronix.de; patchwork-
> lst@pengutronix.de; A.s. Dong <aisheng.dong@nxp.com>; Baruch Siach
> <baruch@tkos.co.il>
> Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> v2:
> - move to freescale folder
> - change compatibles to "fsl" vendor prefix
> - remove unnecessary newlines
> - move status property to be the last in all node
> - remove imx21 compatibles from UART nodes
> - document compatible
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> +++++++++++++++++++++++++
Should this belongs to pinctrl part?
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++
> 3 files changed, 1038 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd705754..85d1c9ec6fa3 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -75,6 +75,10 @@ i.MX6q generic board
> Required root node properties:
> - compatible = "fsl,imx6q";
>
> +i.MX8MQ generic board
> +Required root node properties:
> + - compatible = "fsl,imx8mq";
> +
> Freescale Vybrid Platform Device Tree Bindings
> ----------------------------------------------
>
[...]
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010033>;
> + local-timer-stop;
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> + };
> +
> + A53_0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> + clock-frequency = <8333333>;
Looks strange to me, why set that value?
> + interrupt-parent = <&gic>;
> + arm,no-tick-in-suspend;
> + };
> +
> + peripherals@0 {
Any special purpose to create this?
Regards
Dong Aisheng
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> + bus@30000000 { /* AIPS1 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30000000 0x30000000 0x400000>;
> +
> + gpio1: gpio@30200000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-
> gpio";
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@30210000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-
> gpio";
> + reg = <0x30210000 0x10000>;
> + interrupts = <GIC_SPI 66
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@30220000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-
> gpio";
> + reg = <0x30220000 0x10000>;
> + interrupts = <GIC_SPI 68
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@30230000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-
> gpio";
> + reg = <0x30230000 0x10000>;
> + interrupts = <GIC_SPI 70
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio@30240000 {
> + compatible = "fsl,imx8mq-gpio", "fsl,imx35-
> gpio";
> + reg = <0x30240000 0x10000>;
> + interrupts = <GIC_SPI 72
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + iomuxc: iomuxc@30330000 {
> + compatible = "fsl,imx8mq-iomuxc";
> + reg = <0x30330000 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr@30340000 {
> + compatible = "fsl,imx8mq-iomuxc-gpr",
> "syscon";
> + reg = <0x30340000 0x10000>;
> + };
> +
> + anatop: anatop@30360000 {
> + compatible = "fsl,imx8mq-anatop", "syscon";
> + reg = <0x30360000 0x10000>;
> + interrupts = <GIC_SPI 49
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + clk: clock-controller@30380000 {
> + compatible = "fsl,imx8mq-ccm";
> + reg = <0x30380000 0x10000>;
> + interrupts = <GIC_SPI 85
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> + <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "ckil", "osc_25m", "osc_27m",
> + "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> + };
> +
> + bus@30400000 { /* AIPS2 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30400000 0x30400000 0x400000>;
> + };
> +
> + bus@30800000 { /* AIPS3 */
> + compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30800000 0x30800000 0x400000>;
> +
> + uart1: serial@30860000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> + <&clk IMX8MQ_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial@30880000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> + <&clk IMX8MQ_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial@30890000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> + <&clk IMX8MQ_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@30a20000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a20000 0x10000>;
> + interrupts = <GIC_SPI 35
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@30a30000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a30000 0x10000>;
> + interrupts = <GIC_SPI 36
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@30a40000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a40000 0x10000>;
> + interrupts = <GIC_SPI 37
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@30a50000 {
> + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a50000 0x10000>;
> + interrupts = <GIC_SPI 38
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + uart4: serial@30a60000 {
> + compatible = "fsl,imx8mq-uart",
> + "fsl,imx6q-uart";
> + reg = <0x30a60000 0x10000>;
> + interrupts = <GIC_SPI 29
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> + <&clk IMX8MQ_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: usdhc@30b40000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk
> IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc@30b50000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk
> IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet@30be0000 {
> + compatible = "fsl,imx8mq-fec", "fsl,imx6sx-
> fec";
> + reg = <0x30be0000 0x10000>;
> + interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> + <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> + <&clk
> IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> + clock-names = "ipg", "ahb", "ptp",
> + "enet_clk_ref", "enet_out";
> + fsl,num-tx-queues = <3>;
> + fsl,num-rx-queues = <3>;
> + status = "disabled";
> + };
> + };
> +
> + gic: interrupt-controller@38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base +
> SGI_base) */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> + };
> +};
> --
> 2.15.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-25 10:47 ` A.s. Dong
@ 2018-02-26 3:17 ` Shawn Guo
2018-02-26 6:52 ` A.s. Dong
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-26 3:17 UTC (permalink / raw)
To: A.s. Dong
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel, Lucas Stach
On Sun, Feb 25, 2018 at 10:47:11AM +0000, A.s. Dong wrote:
> > Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> > arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> > +++++++++++++++++++++++++
>
> Should this belongs to pinctrl part?
No. Those pinfunc defines are used by device tree rather than pinctrl
driver.
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-26 3:17 ` Shawn Guo
@ 2018-02-26 6:52 ` A.s. Dong
2018-02-26 7:09 ` Shawn Guo
0 siblings, 1 reply; 31+ messages in thread
From: A.s. Dong @ 2018-02-26 6:52 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel, Lucas Stach
Hi Shawn,
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, February 26, 2018 11:17 AM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>; Mark Rutland
> <mark.rutland@arm.com>; devicetree@vger.kernel.org; Baruch Siach
> <baruch@tkos.co.il>; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; patchwork-lst@pengutronix.de; Rob
> Herring <robh+dt@kernel.org>; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>; linux-
> arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>
> On Sun, Feb 25, 2018 at 10:47:11AM +0000, A.s. Dong wrote:
> > > Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> > > arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> > > +++++++++++++++++++++++++
> >
> > Should this belongs to pinctrl part?
>
> No. Those pinfunc defines are used by device tree rather than pinctrl driver.
>
I had this question because we have below info in the patch
"dt-bindings: add binding for i.MX8MQ IOMUXC":
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
new file mode 100644
index 0000000..5c5d2d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
@@ -0,0 +1,39 @@
...
+ Refer to imx8mq-pinfunc.h in device tree source folder for all available
+ imx8mq PIN_FUNC_ID.
Regards
Dong Aisheng
> Shawn
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-26 6:52 ` A.s. Dong
@ 2018-02-26 7:09 ` Shawn Guo
2018-02-26 8:07 ` A.s. Dong
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2018-02-26 7:09 UTC (permalink / raw)
To: A.s. Dong
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel, Lucas Stach
On Mon, Feb 26, 2018 at 06:52:15AM +0000, A.s. Dong wrote:
> Hi Shawn,
>
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > Sent: Monday, February 26, 2018 11:17 AM
> > To: A.s. Dong <aisheng.dong@nxp.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>; Mark Rutland
> > <mark.rutland@arm.com>; devicetree@vger.kernel.org; Baruch Siach
> > <baruch@tkos.co.il>; Catalin Marinas <catalin.marinas@arm.com>; Will
> > Deacon <will.deacon@arm.com>; patchwork-lst@pengutronix.de; Rob
> > Herring <robh+dt@kernel.org>; dl-linux-imx <linux-imx@nxp.com>;
> > kernel@pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>; linux-
> > arm-kernel@lists.infradead.org
> > Subject: Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
> >
> > On Sun, Feb 25, 2018 at 10:47:11AM +0000, A.s. Dong wrote:
> > > > Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> > > > arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> > > > +++++++++++++++++++++++++
> > >
> > > Should this belongs to pinctrl part?
> >
> > No. Those pinfunc defines are used by device tree rather than pinctrl driver.
> >
>
> I had this question because we have below info in the patch
> "dt-bindings: add binding for i.MX8MQ IOMUXC":
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> new file mode 100644
> index 0000000..5c5d2d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> @@ -0,0 +1,39 @@
> ...
> + Refer to imx8mq-pinfunc.h in device tree source folder for all available
> + imx8mq PIN_FUNC_ID.
This is just a cross reference in document, and should be okay on
different tree during development cycle. If we have the pinfunc header
go via pinctrl tree, we will have a more serious dependency between DT
and pinctrl tree.
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-26 7:09 ` Shawn Guo
@ 2018-02-26 8:07 ` A.s. Dong
0 siblings, 0 replies; 31+ messages in thread
From: A.s. Dong @ 2018-02-26 8:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, dl-linux-imx, kernel,
Fabio Estevam, linux-arm-kernel, Lucas Stach
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, February 26, 2018 3:10 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: Mark Rutland <mark.rutland@arm.com>; devicetree@vger.kernel.org;
> Baruch Siach <baruch@tkos.co.il>; Catalin Marinas
> <catalin.marinas@arm.com>; Will Deacon <will.deacon@arm.com>;
> patchwork-lst@pengutronix.de; Rob Herring <robh+dt@kernel.org>; dl-
> linux-imx <linux-imx@nxp.com>; kernel@pengutronix.de; Fabio Estevam
> <fabio.estevam@nxp.com>; linux-arm-kernel@lists.infradead.org; Lucas
> Stach <l.stach@pengutronix.de>
> Subject: Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>
> On Mon, Feb 26, 2018 at 06:52:15AM +0000, A.s. Dong wrote:
> > Hi Shawn,
> >
> > > -----Original Message-----
> > > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > > Sent: Monday, February 26, 2018 11:17 AM
> > > To: A.s. Dong <aisheng.dong@nxp.com>
> > > Cc: Lucas Stach <l.stach@pengutronix.de>; Mark Rutland
> > > <mark.rutland@arm.com>; devicetree@vger.kernel.org; Baruch Siach
> > > <baruch@tkos.co.il>; Catalin Marinas <catalin.marinas@arm.com>; Will
> > > Deacon <will.deacon@arm.com>; patchwork-lst@pengutronix.de; Rob
> > > Herring <robh+dt@kernel.org>; dl-linux-imx <linux-imx@nxp.com>;
> > > kernel@pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>;
> linux-
> > > arm-kernel@lists.infradead.org
> > > Subject: Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
> > >
> > > On Sun, Feb 25, 2018 at 10:47:11AM +0000, A.s. Dong wrote:
> > > > > Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> > > > > arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> > > > > +++++++++++++++++++++++++
> > > >
> > > > Should this belongs to pinctrl part?
> > >
> > > No. Those pinfunc defines are used by device tree rather than pinctrl
> driver.
> > >
> >
> > I had this question because we have below info in the patch
> > "dt-bindings: add binding for i.MX8MQ IOMUXC":
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > new file mode 100644
> > index 0000000..5c5d2d8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt
> > @@ -0,0 +1,39 @@
> > ...
> > + Refer to imx8mq-pinfunc.h in device tree source folder for all available
> > + imx8mq PIN_FUNC_ID.
>
> This is just a cross reference in document, and should be okay on different
> tree during development cycle. If we have the pinfunc header go via pinctrl
> tree, we will have a more serious dependency between DT and pinctrl tree.
>
Okay, understand now.
Regards
Dong Aisheng
> Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
2018-02-01 18:31 ` [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-25 10:47 ` A.s. Dong
@ 2018-03-09 3:23 ` Shawn Guo
2 siblings, 0 replies; 31+ messages in thread
From: Shawn Guo @ 2018-03-09 3:23 UTC (permalink / raw)
To: Lucas Stach
Cc: Mark Rutland, devicetree, Baruch Siach, Catalin Marinas,
Will Deacon, patchwork-lst, Rob Herring, NXP Linux Team, kernel,
Fabio Estevam, A . s . Dong, linux-arm-kernel
On Thu, Feb 01, 2018 at 07:31:24PM +0100, Lucas Stach wrote:
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
To follow the device naming recommendation from
devicetree-specification, I would suggest a few renames embedded as
below.
https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.2
<snip>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
clock-xxx for node name.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
<snip>
> + usdhc1: usdhc@30b40000 {
s/usdhc/mmc for node name.
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc@30b50000 {
> + compatible = "fsl,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2018-03-09 3:23 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-01 18:31 [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8 Lucas Stach
[not found] ` <20180201183126.32384-1-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-01 18:31 ` [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
[not found] ` <20180201183126.32384-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-02 8:13 ` Jacky Bai
[not found] ` <HE1PR04MB3113FF72B02D642392D625DF87F90-6LN7OEpIatW7Zxc5AHJ2m89NdZoXdze2vxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-02-05 8:45 ` Shawn Guo
2018-02-05 9:07 ` Jacky Bai
2018-02-05 6:09 ` Rob Herring
2018-02-05 15:00 ` Marc Zyngier
2018-02-25 10:47 ` A.s. Dong
2018-02-26 3:17 ` Shawn Guo
2018-02-26 6:52 ` A.s. Dong
2018-02-26 7:09 ` Shawn Guo
2018-02-26 8:07 ` A.s. Dong
2018-03-09 3:23 ` Shawn Guo
2018-02-01 18:31 ` [PATCH v2 3/4] arm64: add support for i.MX8M EVK board Lucas Stach
[not found] ` <20180201183126.32384-3-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2018-02-05 6:09 ` Rob Herring
2018-02-05 7:24 ` Baruch Siach
[not found] ` <20180205072438.nxvhlqk54d7firbz-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
2018-02-05 11:10 ` Lucas Stach
2018-02-23 3:46 ` Shawn Guo
2018-02-23 4:32 ` Baruch Siach
2018-02-23 7:05 ` Shawn Guo
2018-02-23 15:03 ` Shawn Guo
2018-02-23 15:30 ` Juergen Borleis
2018-02-23 15:46 ` Lucas Stach
2018-02-24 2:58 ` Bough Chen
2018-02-24 6:00 ` Shawn Guo
2018-02-25 9:54 ` A.s. Dong
2018-02-23 15:45 ` Lucas Stach
2018-02-25 10:00 ` A.s. Dong
2018-02-01 18:31 ` [PATCH v2 4/4] MAINTAINERS: add i.MX8 DT path to i.MX architecture Lucas Stach
2018-02-23 14:56 ` [PATCH v2 1/4] arm64: add basic Kconfig symbols for i.MX8 Shawn Guo
2018-02-25 10:17 ` A.s. Dong
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