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Wed, 11 Dec 2019 05:23:01 +0000 From: "Tan, Ley Foon" To: Masahiro Yamada , "linux-mtd@lists.infradead.org" CC: Dinh Nguyen , Marek Vasut , "Mark Rutland" , Miquel Raynal , Philipp Zabel , Richard Weinberger , Rob Herring , Vignesh Raghavendra , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] mtd: rawnand: denali: add reset controlling Thread-Topic: [PATCH] mtd: rawnand: denali: add reset controlling Thread-Index: AQHVrzs7tJZlV61iv0eN4nwl1EYnh6e0Zffg Date: Wed, 11 Dec 2019 05:23:01 +0000 Message-ID: References: <20191210091453.26346-1-yamada.masahiro@socionext.com> In-Reply-To: <20191210091453.26346-1-yamada.masahiro@socionext.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjFjY2E2NWItZTFhYS00ODM3LWI4MzItNTNiYWFhZTJjMDcyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieGZsbEorY1dVbWxzemhVb0doQVlXb3V3SHdFXC91V3RqMjYya2FmVERSRWFQQzZHYlNBeDFlSURNOFlCVStwa1UifQ== dlp-reaction: no-action dlp-version: 11.2.0.6 dlp-product: dlpe-windows x-ctpclassification: CTP_NT authentication-results: spf=none (sender IP is ) smtp.mailfrom=ley.foon.tan@intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d57b9dc7-5437-4359-38b4-08d77dfa312c X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Dec 2019 05:23:01.2224 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +gqfMEBN44qYmhvimNRkqnRPl1wAppVnjZD/4VfwrhgHnYWvkctJJGbKdWVCwGxbt4sI+2MgeVzPjyq9WcGsqA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4381 X-OriginatorOrg: intel.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org > -----Original Message----- > From: Masahiro Yamada > Sent: Tuesday, December 10, 2019 5:15 PM > To: linux-mtd@lists.infradead.org > Cc: Dinh Nguyen ; Marek Vasut ; > Tan, Ley Foon ; Masahiro Yamada > ; Mark Rutland > ; Miquel Raynal ; > Philipp Zabel ; Richard Weinberger > ; Rob Herring ; Vignesh > Raghavendra ; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: [PATCH] mtd: rawnand: denali: add reset controlling >=20 > According to the Denali User's Guide, this IP has two reset signals. >=20 > rst_n: reset most of FFs in the controller core > reg_rst_n: reset all FFs in the register interface, and in the > initialization sequence >=20 > This commit supports controlling those reset signals, although they might= be > often tied up together in actual SoC integration. >=20 > One thing that should be kept in mind is the automated initialization > sequence (a.k.a. 'bootstrap' process) is kicked off when reg_rst_n is > deasserted. >=20 > When the reset is deasserted, the controller issues a RESET command to th= e > chip select 0, and attempts to read out the chip ID, and further more, ON= FI > parameters if it is an ONFI-compliant device. Then, the controller sets u= p the > relevant registers based on the detected device parameters. >=20 > This process is just redundant for Linux because nand_scan_ident() probes > devices and sets up parameters accordingly. Rather, this hardware feature= is > annoying because it ends up with misdetection due to bugs. >=20 > So, commit 0615e7ad5d52 ("mtd: nand: denali: remove Toshiba and Hynix > specific fixup code") changed the driver to not rely on it. >=20 > However, there is no way to prevent it from running. The IP provides the > 'bootstrap_inhibit_init' port to suppress this sequence, but it is usuall= y out of > software control, and dependent on SoC implementation. > As for the Socionext UniPhier platform, LD4 always enables it. For the la= ter > SoCs, the bootstrap sequence runs depending on the boot mode. >=20 > I added usleep_range() to make the driver wait until the sequence finishe= s. > Otherwise, the driver would fail to detect the chip due to the race betwe= en > the driver and hardware-controlled sequence. >=20 > Signed-off-by: Masahiro Yamada > --- >=20 > .../devicetree/bindings/mtd/denali-nand.txt | 7 ++++ > drivers/mtd/nand/raw/denali_dt.c | 40 ++++++++++++++++++- > 2 files changed, 46 insertions(+), 1 deletion(-) >=20 > diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt > b/Documentation/devicetree/bindings/mtd/denali-nand.txt > index b32aed1db46d..a48b17fb969a 100644 > --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt > +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt > @@ -14,6 +14,11 @@ Required properties: > interface clock, and the ECC circuit clock. > - clock-names: should contain "nand", "nand_x", "ecc" >=20 > +Optional properties: > + - resets: may contain phandles to the controller core reset, the > +register reset > + - reset-names: may contain "nand", "reg" > + > Sub-nodes: > Sub-nodes represent available NAND chips. >=20 > @@ -46,6 +51,8 @@ nand: nand@ff900000 { > reg-names =3D "nand_data", "denali_reg"; > clocks =3D <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; > clock-names =3D "nand", "nand_x", "ecc"; > + resets =3D <&nand_rst>, <&nand_reg_rst>; > + reset-names =3D "nand", "reg"; > interrupts =3D <0 144 4>; >=20 > nand@0 { > diff --git a/drivers/mtd/nand/raw/denali_dt.c > b/drivers/mtd/nand/raw/denali_dt.c > index 8b779a899dcf..132bc6cc066c 100644 > --- a/drivers/mtd/nand/raw/denali_dt.c > +++ b/drivers/mtd/nand/raw/denali_dt.c > @@ -6,6 +6,7 @@ > */ >=20 > #include > +#include > #include > #include > #include > @@ -14,6 +15,7 @@ > #include > #include > #include > +#include >=20 > #include "denali.h" >=20 > @@ -22,6 +24,8 @@ struct denali_dt { > struct clk *clk; /* core clock */ > struct clk *clk_x; /* bus interface clock */ > struct clk *clk_ecc; /* ECC circuit clock */ > + struct reset_control *rst; /* core reset */ > + struct reset_control *rst_reg; /* register reset */ > }; >=20 > struct denali_dt_data { > @@ -151,6 +155,14 @@ static int denali_dt_probe(struct platform_device > *pdev) > if (IS_ERR(dt->clk_ecc)) > return PTR_ERR(dt->clk_ecc); >=20 > + dt->rst =3D devm_reset_control_get_optional_shared(dev, "nand"); > + if (IS_ERR(dt->rst)) > + return PTR_ERR(dt->rst); > + > + dt->rst_reg =3D devm_reset_control_get_optional_shared(dev, "reg"); > + if (IS_ERR(dt->rst_reg)) > + return PTR_ERR(dt->rst_reg); Will it trigger error if dts doesn't have "nand" or "reg" for reset-name? SOCFPGA dts doesn't have this. > + > ret =3D clk_prepare_enable(dt->clk); > if (ret) > return ret; > @@ -166,10 +178,30 @@ static int denali_dt_probe(struct platform_device > *pdev) > denali->clk_rate =3D clk_get_rate(dt->clk); > denali->clk_x_rate =3D clk_get_rate(dt->clk_x); >=20 > - ret =3D denali_init(denali); > + /* > + * Deassert the register reset, and the core reset in this order. > + * Deasserting the core reset while the register reset is asserted > + * will cause unpredictable behavior in the controller. > + */ > + ret =3D reset_control_deassert(dt->rst_reg); > if (ret) > goto out_disable_clk_ecc; >=20 > + ret =3D reset_control_deassert(dt->rst); > + if (ret) > + goto out_assert_rst_reg; > + > + /* > + * When the reset is deasserted, the initialization sequence is kicked > + * (bootstrap process). This will take a while, and the driver must > + * wait until it finished in order to avoid unpredictable behavior. > + */ > + usleep_range(200, 1000); > + > + ret =3D denali_init(denali); > + if (ret) > + goto out_assert_rst; > + > for_each_child_of_node(dev->of_node, np) { > ret =3D denali_dt_chip_init(denali, np); > if (ret) { > @@ -184,6 +216,10 @@ static int denali_dt_probe(struct platform_device > *pdev) >=20 > out_remove_denali: > denali_remove(denali); > +out_assert_rst: > + reset_control_assert(dt->rst); > +out_assert_rst_reg: > + reset_control_assert(dt->rst_reg); > out_disable_clk_ecc: > clk_disable_unprepare(dt->clk_ecc); > out_disable_clk_x: > @@ -199,6 +235,8 @@ static int denali_dt_remove(struct platform_device > *pdev) > struct denali_dt *dt =3D platform_get_drvdata(pdev); >=20 > denali_remove(&dt->controller); > + reset_control_assert(dt->rst); > + reset_control_assert(dt->rst_reg); > clk_disable_unprepare(dt->clk_ecc); > clk_disable_unprepare(dt->clk_x); > clk_disable_unprepare(dt->clk); > -- > 2.17.1