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Sun, 18 Jul 2021 08:29:02 +0000 From: Biju Das To: Rob Herring , Geert Uytterhoeven CC: Kishon Vijay Abraham I , Vinod Koul , Yoshihiro Shimoda , "linux-phy@lists.infradead.org" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , Linux-Renesas Subject: RE: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Thread-Topic: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Thread-Index: AQHXbYHhglWpoTGXsUeqWuHX3BdNeassSd4AgBbHkICABXCBgA== Date: Sun, 18 Jul 2021 08:29:01 +0000 Message-ID: References: <20210630073013.22415-1-biju.das.jz@bp.renesas.com> <20210630073013.22415-8-biju.das.jz@bp.renesas.com> <20210714212135.GA3539572@robh.at.kernel.org> In-Reply-To: <20210714212135.GA3539572@robh.at.kernel.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OS0PR01MB5922.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41961b29-0ca4-4759-627a-08d949c61932 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jul 2021 08:29:02.0060 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LTqOtMIsiY4k4EuQwrx9+3of84DAmQhLigxZ92x2C2/nv/xiG12qDtAT0Mwo0jrzQuGU3NJBZkPwyVXVRIJXrrN2BGQAMzzqKhQCZYfxN6M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSAPR01MB2530 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Rob, > -----Original Message----- > Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Documen= t > RZ/G2L phy bindings >=20 > On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote: > > Hi Biju, > > > > Thanks for your patch! > > > > On Wed, Jun 30, 2021 at 9:31 AM Biju Das > wrote: > > > Document USB phy bindings for RZ/G2L SoC. > > > > > > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. > > > Apart from this it uses a different OTG-BC interrupt bit for device > recognition. > > > > Nothing about resets? But see below... > > > > > > > > Signed-off-by: Biju Das > > > Reviewed-by: Lad Prabhakar > > > --- > > > v2->v3 > > > * Created a new compatible for RZ/G2L as per Geert's suggestion. > > > * Added resets required properties for RZ/G2L SoC. > > > --- > > > .../bindings/phy/renesas,usb2-phy.yaml | 18 > ++++++++++++++++++ > > > 1 file changed, 18 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml > > > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml > > > index d5dc5a3cdceb..a7e585ff28dc 100644 > > > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml > > > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml > > > @@ -30,6 +30,9 @@ properties: > > > - renesas,usb2-phy-r8a77995 # R-Car D3 > > > - const: renesas,rcar-gen3-usb2-phy > > > > > > + - items: > > > + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} > > > + > > > reg: > > > maxItems: 1 > > > > > > @@ -91,6 +94,21 @@ required: > > > - clocks > > > - '#phy-cells' > > > > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: renesas,usb2-phy-r9a07g044 > > > + then: > > > + properties: > > > + resets: > > > + items: > > > + - description: USB phy reset > > > + - description: reset of USB 2.0 host side > > > > Do you need the second reset? > > Looking at your .dtsi patch, the second reset is shared with > > ehci/ohci, so perhaps it makes sense to drop it from the phy node? >=20 > The existing binding has the host reset (and peripheral, but no phy > reset). Was that a mistake too? Smells like collecting resources the > driver happens to want, not what the h/w connections are. On that SoC's there is no USBPHY control IP to control the reset. But PHY is part of either host block or peripheral block. On RZ/G2L as well PHY is part of Host block but we have dedicated IP to control the reset. Regards, Biju