From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C50ADC07E95 for ; Sun, 4 Jul 2021 09:31:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96CC2613E9 for ; Sun, 4 Jul 2021 09:31:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229499AbhGDJea (ORCPT ); Sun, 4 Jul 2021 05:34:30 -0400 Received: from ixit.cz ([94.230.151.217]:55418 "EHLO ixit.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbhGDJea (ORCPT ); Sun, 4 Jul 2021 05:34:30 -0400 Received: from [192.168.1.138] (ixit.cz [94.230.151.217]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ixit.cz (Postfix) with ESMTPSA id DE3B823B1D; Sun, 4 Jul 2021 11:31:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ixit.cz; s=dkim; t=1625391114; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=W1g41h8Fs4lJKHljV9Uq64GlawCyLUePGmIHjM31M6c=; b=vGiHUtF9tBOLHgI8H4RxPF+DiSowuCPZ/pcyuKhlPaGpAWFUVdLPZMyx9qPTdpPQlNFni2 iYv0c1xzdmoDo9r6NCuaNgouUWz01dFNumwte887igxJnpDbpNIFjVvTcjIr7rcvywkKE/ 6IqBFKwyNN+1SlxBv18QO8JlOWMmwyA= Date: Sun, 04 Jul 2021 11:31:06 +0200 From: David Heidelberg Subject: Re: [PATCH] RFC: dt-bindings: drm/msm/gpu: convert to YAML To: Dmitry Baryshkov Cc: Sharat Masetty , masneyb@onstation.org, Rob Clark , Jordan Crouse , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS Message-Id: In-Reply-To: References: <20210703151835.171313-1-david@ixit.cz> X-Mailer: geary/40.0 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Thank you Dmitry, I'll fix it for [v2]. I'll wait a little bit for some feedback now. Best regards David Heidelberg On Sun, Jul 4 2021 at 11:18:36 +0300, Dmitry Baryshkov wrote: > On Sat, 3 Jul 2021 at 18:19, David Heidelberg wrote: >> >> This warning cannot be fixed by conversion, since this naming is >> already used. >> Documentation/devicetree/bindings/display/msm/gpu.example.dt.yaml: >> gpu@5000000: interconnect-names: ['gfx-mem'] is too short > > It is not a problem of the name length. You've declared that > interconnect-names would contain two items (gfx-mem and ocmem), but > add just one. > >> >> Signed-off-by: David Heidelberg >> --- >> .../devicetree/bindings/display/msm/gpu.txt | 157 ----------- >> .../devicetree/bindings/display/msm/gpu.yaml | 256 >> ++++++++++++++++++ >> 2 files changed, 256 insertions(+), 157 deletions(-) >> delete mode 100644 >> Documentation/devicetree/bindings/display/msm/gpu.txt >> create mode 100644 >> Documentation/devicetree/bindings/display/msm/gpu.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt >> b/Documentation/devicetree/bindings/display/msm/gpu.txt >> deleted file mode 100644 >> index 090dcb3fc34d..000000000000 >> --- a/Documentation/devicetree/bindings/display/msm/gpu.txt >> +++ /dev/null >> @@ -1,157 +0,0 @@ >> -Qualcomm adreno/snapdragon GPU >> - >> -Required properties: >> -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or >> - "amd,imageon-XYZ.W", "amd,imageon" >> - for example: "qcom,adreno-306.0", "qcom,adreno" >> - Note that you need to list the less specific "qcom,adreno" >> (since this >> - is what the device is matched on), in addition to the more >> specific >> - with the chip-id. >> - If "amd,imageon" is used, there should be no top level msm >> device. >> -- reg: Physical base address and length of the controller's >> registers. >> -- interrupts: The interrupt signal from the gpu. >> -- clocks: device clocks (if applicable) >> - See ../clocks/clock-bindings.txt for details. >> -- clock-names: the following clocks are required by a3xx, a4xx and >> a5xx >> - cores: >> - * "core" >> - * "iface" >> - * "mem_iface" >> - For GMU attached devices the GPU clocks are not used and are not >> required. The >> - following devices should not list clocks: >> - - qcom,adreno-630.2 >> -- iommus: optional phandle to an adreno iommu instance >> -- operating-points-v2: optional phandle to the OPP operating points >> -- interconnects: optional phandle to an interconnect provider. See >> - ../interconnect/interconnect.txt for details. Some A3xx and all >> A4xx platforms >> - will have two paths; all others will have one path. >> -- interconnect-names: The names of the interconnect paths that >> correspond to the >> - interconnects property. Values must be gfx-mem and ocmem. >> -- qcom,gmu: For GMU attached devices a phandle to the GMU device >> that will >> - control the power for the GPU. Applicable targets: >> - - qcom,adreno-630.2 >> -- zap-shader: For a5xx and a6xx devices this node contains a >> memory-region that >> - points to reserved memory to store the zap shader that can be >> used to help >> - bring the GPU out of secure mode. >> -- firmware-name: optional property of the 'zap-shader' node, >> listing the >> - relative path of the device specific zap firmware. >> -- sram: phandle to the On Chip Memory (OCMEM) that's present on >> some a3xx and >> - a4xx Snapdragon SoCs. See >> - Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. >> - >> -Optional properties: >> -- #cooling-cells: The value must be 2. For details, please refer >> - >> Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. >> - >> -Example 3xx/4xx: >> - >> -/ { >> - ... >> - >> - gpu: adreno@fdb00000 { >> - compatible = "qcom,adreno-330.2", >> - "qcom,adreno"; >> - reg = <0xfdb00000 0x10000>; >> - reg-names = "kgsl_3d0_reg_memory"; >> - interrupts = ; >> - interrupt-names = "kgsl_3d0_irq"; >> - clock-names = "core", >> - "iface", >> - "mem_iface"; >> - clocks = <&mmcc OXILI_GFX3D_CLK>, >> - <&mmcc OXILICX_AHB_CLK>, >> - <&mmcc OXILICX_AXI_CLK>; >> - sram = <&gpu_sram>; >> - power-domains = <&mmcc OXILICX_GDSC>; >> - operating-points-v2 = <&gpu_opp_table>; >> - iommus = <&gpu_iommu 0>; >> - #cooling-cells = <2>; >> - }; >> - >> - gpu_sram: ocmem@fdd00000 { >> - compatible = "qcom,msm8974-ocmem"; >> - >> - reg = <0xfdd00000 0x2000>, >> - <0xfec00000 0x180000>; >> - reg-names = "ctrl", >> - "mem"; >> - >> - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, >> - <&mmcc OCMEMCX_OCMEMNOC_CLK>; >> - clock-names = "core", >> - "iface"; >> - >> - #address-cells = <1>; >> - #size-cells = <1>; >> - >> - gpu_sram: gpu-sram@0 { >> - reg = <0x0 0x100000>; >> - ranges = <0 0 0xfec00000 0x100000>; >> - }; >> - }; >> -}; >> - >> -Example a6xx (with GMU): >> - >> -/ { >> - ... >> - >> - gpu@5000000 { >> - compatible = "qcom,adreno-630.2", "qcom,adreno"; >> - #stream-id-cells = <16>; >> - >> - reg = <0x5000000 0x40000>, <0x509e000 0x10>; >> - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; >> - >> - #cooling-cells = <2>; >> - >> - /* >> - * Look ma, no clocks! The GPU clocks and power are >> - * controlled entirely by the GMU >> - */ >> - >> - interrupts = ; >> - >> - iommus = <&adreno_smmu 0>; >> - >> - operating-points-v2 = <&gpu_opp_table>; >> - >> - interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos >> SLAVE_EBI1>; >> - interconnect-names = "gfx-mem"; >> - >> - gpu_opp_table: opp-table { >> - compatible = "operating-points-v2"; >> - >> - opp-430000000 { >> - opp-hz = /bits/ 64 <430000000>; >> - opp-level = >> ; >> - opp-peak-kBps = <5412000>; >> - }; >> - >> - opp-355000000 { >> - opp-hz = /bits/ 64 <355000000>; >> - opp-level = >> ; >> - opp-peak-kBps = <3072000>; >> - }; >> - >> - opp-267000000 { >> - opp-hz = /bits/ 64 <267000000>; >> - opp-level = >> ; >> - opp-peak-kBps = <3072000>; >> - }; >> - >> - opp-180000000 { >> - opp-hz = /bits/ 64 <180000000>; >> - opp-level = >> ; >> - opp-peak-kBps = <1804000>; >> - }; >> - }; >> - >> - qcom,gmu = <&gmu>; >> - >> - zap-shader { >> - memory-region = <&zap_shader_region>; >> - firmware-name = >> "qcom/LENOVO/81JL/qcdxkmsuc850.mbn" >> - }; >> - }; >> -}; >> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml >> b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> new file mode 100644 >> index 000000000000..4315482e0b12 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> @@ -0,0 +1,256 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> + >> +$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Devicetree bindings for the Adreno or Snapdragon GPUs >> + >> +maintainers: >> + - Rob Clark >> + >> +description: | >> + These bindings describe the GPUs >> + >> +properties: >> + compatible: >> + anyOf: >> + - items: >> + - pattern: '^qcom,adreno-[3-6][0-9][0-9].[0-9]$' >> + - const: qcom,adreno >> + - items: >> + - pattern: '^amd,imageon-200.[0-1]$' >> + - const: amd,imageon >> + >> + clocks: >> + maxItems: 3 >> + >> + clock-names: >> + maxItems: 3 >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 >> + description: Physical base address and length of the >> controller's registers. >> + >> + reg-names: >> + minItems: 1 >> + maxItems: 2 >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-names: >> + maxItems: 1 >> + >> + interconnects: >> + minItems: 1 >> + maxItems: 2 >> + description: | >> + optional phandle to an interconnect provider. See >> + ../interconnect/interconnect.txt for details. >> + Some A3xx and all A4xx platforms will have two paths; >> + all others will have one path. >> + >> + interconnect-names: >> + items: >> + - const: gfx-mem >> + - const: ocmem >> + description: | >> + the names of the interconnect paths that correspond to >> + the interconnects property >> + >> + iommus: >> + maxItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + minItems: 1 >> + maxItems: 4 >> + description: | >> + phandles to one or more reserved on-chip SRAM regions. >> + phandle to the On Chip Memory (OCMEM) that's present on some >> a3xx and >> + a4xx Snapdragon SoCs. See >> + Documentation/devicetree/bindings/sram/qcom,ocmem.yaml >> + >> + operating-points-v2: true >> + opp-table: true >> + >> + power-domains: >> + maxItems: 1 >> + >> + zap-shader: >> + description: | >> + For a5xx and a6xx devices this node contains a memory-region >> that >> + points to reserved memory to store the zap shader that can >> be used to >> + help bring the GPU out of secure mode. >> + >> + "#cooling-cells": >> + const: 2 >> + description: | >> + For details, please refer >> + >> Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml >> + >> + qcom,gmu: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: | >> + for GMU attached devices a phandle to the GMU device that >> will >> + control the power for the GPU >> + >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + >> +additionalProperties: false >> + >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + pattern: '^qcom,adreno-[3-5][0-9][0-9].[0-9]$' >> + >> + then: >> + properties: >> + clocks: >> + items: >> + - description: GPU Core clock >> + - description: GPU Interface clock >> + - description: GPU Memory Interface clock >> + >> + clock-names: >> + items: >> + - const: core >> + - const: iface >> + - const: mem_iface >> + required: >> + - clocks >> + - clock-names >> + >> +examples: >> + - | >> + >> + // Example a3xx/4xx: >> + >> + #include >> + #include >> + #include >> + #include >> + >> + gpu: adreno@fdb00000 { >> + compatible = "qcom,adreno-330.2", "qcom,adreno"; >> + >> + reg = <0xfdb00000 0x10000>; >> + reg-names = "kgsl_3d0_reg_memory"; >> + >> + clock-names = "core", "iface", "mem_iface"; >> + clocks = <&mmcc OXILI_GFX3D_CLK>, >> + <&mmcc OXILICX_AHB_CLK>, >> + <&mmcc OXILICX_AXI_CLK>; >> + >> + interrupts = ; >> + interrupt-names = "kgsl_3d0_irq"; >> + >> + sram = <&gpu_sram>; >> + power-domains = <&mmcc OXILICX_GDSC>; >> + operating-points-v2 = <&gpu_opp_table>; >> + iommus = <&gpu_iommu 0>; >> + #cooling-cells = <2>; >> + }; >> + >> + ocmem@fdd00000 { >> + compatible = "qcom,msm8974-ocmem"; >> + >> + reg = <0xfdd00000 0x2000>, >> + <0xfec00000 0x180000>; >> + reg-names = "ctrl", "mem"; >> + >> + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, >> + <&mmcc OCMEMCX_OCMEMNOC_CLK>; >> + clock-names = "core", "iface"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0xfec00000 0x100000>; >> + >> + gpu_sram: gpu-sram@0 { >> + reg = <0x0 0x100000>; >> + }; >> + }; >> + - | >> + >> + // Example a6xx (with GMU): >> + >> + #include >> + #include >> + #include >> + #include >> + #include >> + #include >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + zap_shader_region: gpu@8f200000 { >> + compatible = "shared-dma-pool"; >> + reg = <0x0 0x90b00000 0x0 0xa00000>; >> + no-map; >> + }; >> + }; >> + >> + gpu@5000000 { >> + compatible = "qcom,adreno-630.2", "qcom,adreno"; >> + >> + reg = <0x5000000 0x40000>, <0x509e000 0x10>; >> + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; >> + >> + #cooling-cells = <2>; >> + >> + interrupts = ; >> + >> + iommus = <&adreno_smmu 0>; >> + >> + operating-points-v2 = <&gpu_opp_table>; >> + >> + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos >> SLAVE_EBI1>; >> + interconnect-names = "gfx-mem"; >> + >> + qcom,gmu = <&gmu>; >> + >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-430000000 { >> + opp-hz = /bits/ 64 <430000000>; >> + opp-level = ; >> + opp-peak-kBps = <5412000>; >> + }; >> + >> + opp-355000000 { >> + opp-hz = /bits/ 64 <355000000>; >> + opp-level = ; >> + opp-peak-kBps = <3072000>; >> + }; >> + >> + opp-267000000 { >> + opp-hz = /bits/ 64 <267000000>; >> + opp-level = ; >> + opp-peak-kBps = <3072000>; >> + }; >> + >> + opp-180000000 { >> + opp-hz = /bits/ 64 <180000000>; >> + opp-level = ; >> + opp-peak-kBps = <1804000>; >> + }; >> + }; >> + >> + zap-shader { >> + memory-region = <&zap_shader_region>; >> + firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; >> + }; >> + }; >> -- >> 2.30.2 >> > > > -- > With best wishes > Dmitry