* [PATCH v3 0/6] add NXP imx8mp usb support
@ 2020-09-22 10:46 Li Jun
2020-09-22 10:46 ` [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support Li Jun
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
logic to support low power, this wakeup logic has a separated interrupt
which can generate events with suspend clock(32K); due to SoC integration
limitation, a few quriks required, instead of create new properties flags,
introduce platform data and pass it from glue layer to dwc3 core, those xhci
private data can further pass to xhci-plat.
changes for v3:
- Add dwc3 core related clocks into dwc3 core node, and glue layer driver
only handle the clocks(hsio and suspend) for glue block, this is to
match real HW.
- Change to use property "xhci-64bit-support-disable" to disable 64bit DMA
as imx8mp USB integration actully can't support it, so remove platform
data in v2.
- Some changes of imx8mp usb driver binding doc to address comments from Rob
Changes for v2:
- Drop the 2 patches for new property("snps,xhci-dis-64bit-support-quirk")
introduction, as suggested, imply by SoC compatible string, this is done
by introduce dwc3 core platform data and pass the xhci_plat_priv to
xhci-plat for those xhci quirks, so a new patch added:
[1/5] usb: dwc3: add platform data to dwc3 core device to pass data.
this patch is based on Peter's one patch which is also in review:
https://patchwork.kernel.org/patch/11640945/
- dts change, use the USB power function of TRL logic instead of a always-on
regulator to control vbus on/off.
- Some changes to address Peter's command on patch [2/5].
Li Jun (6):
dt-bindings: usb: xhci: add property to disable xhci 64bit support
usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via
property
dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
usb: dwc3: add imx8mp dwc3 glue layer driver
arm64: dtsi: imx8mp: add usb nodes
arm64: dts: imx8mp-evk: enable usb1 as host mode
.../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99 ++++++
Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 ++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++
drivers/usb/dwc3/Kconfig | 10 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-imx8mp.c | 363 +++++++++++++++++++++
drivers/usb/host/xhci-plat.c | 4 +
8 files changed, 589 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c
--
2.7.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
@ 2020-09-22 10:46 ` Li Jun
2020-09-29 18:11 ` Rob Herring
2020-09-22 10:46 ` [PATCH v3 2/6] usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via property Li Jun
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
Add a property "xhci-64bit-support-disable" to disable xhci 64bit address
dma, some SoC integration may not support 64bit DMA but the AC64 bit
(bit 0) of HCCPARAMS1 is kept to be 1.
Signed-off-by: Li Jun <jun.li@nxp.com>
---
Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 0c5cff8..26446fb 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -28,6 +28,9 @@ Optional properties:
- quirk-broken-port-ped: set if the controller has broken port disable mechanism
- imod-interval-ns: default interrupt moderation interval is 5000ns
- phys : see usb-hcd.yaml in the current directory
+ - xhci-64bit-support-disable: set if the AC64 bit (bit 0) of HCCPARAMS1 is
+ set to be 1, but the controller actually can't handle 64-bit address
+ due to SoC integration.
additionally the properties from usb-hcd.yaml (in the current directory) are
supported.
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/6] usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via property
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
2020-09-22 10:46 ` [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support Li Jun
@ 2020-09-22 10:46 ` Li Jun
2020-09-22 10:46 ` [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
` (3 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
Some OF platforms may also have the problem AC64 bit (bit 0)
of HCCPARAMS1 set to be 1 but the controller actually can't support
64-bit address when SoC integration, so enable XHCI_NO_64BIT_SUPPORT
via dts property "xhci-64bit-support-disable".
Signed-off-by: Li Jun <jun.li@nxp.com>
---
drivers/usb/host/xhci-plat.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 3057cfc..2b63c8b 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -300,6 +300,10 @@ static int xhci_plat_probe(struct platform_device *pdev)
device_property_read_u32(tmpdev, "imod-interval-ns",
&xhci->imod_interval);
+
+ if (device_property_read_bool(tmpdev,
+ "xhci-64bit-support-disable"))
+ xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
}
hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 0);
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
2020-09-22 10:46 ` [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support Li Jun
2020-09-22 10:46 ` [PATCH v3 2/6] usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via property Li Jun
@ 2020-09-22 10:46 ` Li Jun
2020-09-22 14:32 ` Krzysztof Kozlowski
2020-09-22 10:46 ` [PATCH v3 4/6] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
to support low power mode, the glue layer is for this wakeup
functionality, which has a separated interrupt, can support
wakeup from U3 and connect events for host, and vbus wakeup for
device.
Signed-off-by: Li Jun <jun.li@nxp.com>
---
.../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99 ++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
new file mode 100644
index 0000000..a5d5566
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP iMX8MP Soc USB Controller
+
+maintainers:
+ - Li Jun <jun.li@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mp-dwc3
+
+ reg:
+ maxItems: 1
+ description: Address and length of the register set for the wrapper of
+ dwc3 core on the SOC.
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ interrupts:
+ maxItems: 1
+ description: The interrupt that is asserted when a wakeup event is
+ received.
+
+ clocks:
+ description:
+ A list of phandle and clock-specifier pairs for the clocks
+ listed in clock-names.
+ items:
+ - description: system hsio root clock.
+ - description: suspend clock, used for usb wakeup logic.
+
+ clock-names:
+ items:
+ - const: hsio
+ - const: suspend
+
+# Required child node:
+
+patternProperties:
+ "^dwc3@[0-9a-f]+$":
+ type: object
+ description:
+ A child node must exist to represent the core DWC3 IP block
+ The content of the node is defined in dwc3.txt.
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ usb3_0: usb@32f10100 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10100 0x8>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dwc3@38100000 {
+ compatible = "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/6] usb: dwc3: add imx8mp dwc3 glue layer driver
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
` (2 preceding siblings ...)
2020-09-22 10:46 ` [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
@ 2020-09-22 10:46 ` Li Jun
2020-09-22 10:46 ` [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes Li Jun
2020-09-22 10:46 ` [PATCH v3 6/6] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
5 siblings, 0 replies; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
imx8mp SoC integrate dwc3 3.30b IP and has some customizations to
support low power, which has a seprated wakeup irq and additional
logic to wakeup usb from low power mode both for host mode and
device mode.
Signed-off-by: Li Jun <jun.li@nxp.com>
---
drivers/usb/dwc3/Kconfig | 10 ++
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-imx8mp.c | 363 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 374 insertions(+)
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 7a23045..2133acf 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -139,4 +139,14 @@ config USB_DWC3_QCOM
for peripheral mode support.
Say 'Y' or 'M' if you have one such device.
+config USB_DWC3_IMX8MP
+ tristate "NXP iMX8MP Platform"
+ depends on OF && COMMON_CLK
+ depends on (ARCH_MXC && ARM64) || COMPILE_TEST
+ default USB_DWC3
+ help
+ NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
+ functionality.
+ Say 'Y' or 'M' if you have one such device.
+
endif
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index ae86da0..2259f88 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o
obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o
+obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c b/drivers/usb/dwc3/dwc3-imx8mp.c
new file mode 100644
index 0000000..75f0042
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-imx8mp.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
+ *
+ * Copyright (c) 2020 NXP.
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "core.h"
+
+/* USB wakeup registers */
+#define USB_WAKEUP_CTRL 0x00
+
+/* Global wakeup interrupt enable, also used to clear interrupt */
+#define USB_WAKEUP_EN BIT(31)
+/* Wakeup from connect or disconnect, only for superspeed */
+#define USB_WAKEUP_SS_CONN BIT(5)
+/* 0 select vbus_valid, 1 select sessvld */
+#define USB_WAKEUP_VBUS_SRC_SESS_VAL BIT(4)
+/* Enable signal for wake up from u3 state */
+#define USB_WAKEUP_U3_EN BIT(3)
+/* Enable signal for wake up from id change */
+#define USB_WAKEUP_ID_EN BIT(2)
+/* Enable signal for wake up from vbus change */
+#define USB_WAKEUP_VBUS_EN BIT(1)
+/* Enable signal for wake up from dp/dm change */
+#define USB_WAKEUP_DPDM_EN BIT(0)
+
+#define USB_WAKEUP_EN_MASK GENMASK(5, 0)
+
+struct dwc3_imx8mp {
+ struct device *dev;
+ struct platform_device *dwc3;
+ void __iomem *glue_base;
+ struct clk *hsio_clk;
+ struct clk *suspend_clk;
+ int irq;
+ bool pm_suspended;
+ bool wakeup_pending;
+};
+
+static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx)
+{
+ struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3);
+ u32 val;
+
+ if (!dwc3)
+ return;
+
+ val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+
+ if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci)
+ val |= USB_WAKEUP_EN | USB_WAKEUP_SS_CONN |
+ USB_WAKEUP_U3_EN | USB_WAKEUP_DPDM_EN;
+ else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+ val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN |
+ USB_WAKEUP_VBUS_SRC_SESS_VAL;
+
+ writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static void dwc3_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc3_imx)
+{
+ u32 val;
+
+ val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+ val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK);
+ writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL);
+}
+
+static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc3_imx)
+{
+ struct dwc3_imx8mp *dwc3_imx = _dwc3_imx;
+ struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3);
+
+ if (!dwc3_imx->pm_suspended)
+ return IRQ_HANDLED;
+
+ disable_irq_nosync(dwc3_imx->irq);
+ dwc3_imx->wakeup_pending = true;
+
+ if ((dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc->xhci)
+ pm_runtime_resume(&dwc->xhci->dev);
+ else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
+ pm_runtime_get(dwc->dev);
+
+ return IRQ_HANDLED;
+}
+
+static int dwc3_imx8mp_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *dwc3_np, *node = dev->of_node;
+ struct dwc3_imx8mp *dwc3_imx;
+ int err, irq;
+
+ if (!node) {
+ dev_err(dev, "device node not found\n");
+ return -EINVAL;
+ }
+
+ dwc3_imx = devm_kzalloc(dev, sizeof(*dwc3_imx), GFP_KERNEL);
+ if (!dwc3_imx)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, dwc3_imx);
+
+ dwc3_imx->dev = dev;
+
+ dwc3_imx->glue_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dwc3_imx->glue_base))
+ return PTR_ERR(dwc3_imx->glue_base);
+
+ dwc3_imx->hsio_clk = devm_clk_get(dev, "hsio");
+ if (IS_ERR(dwc3_imx->hsio_clk)) {
+ err = PTR_ERR(dwc3_imx->hsio_clk);
+ dev_err(dev, "Failed to get hsio clk, err=%d\n", err);
+ return err;
+ }
+
+ err = clk_prepare_enable(dwc3_imx->hsio_clk);
+ if (err) {
+ dev_err(dev, "Failed to enable hsio clk, err=%d\n", err);
+ return err;
+ }
+
+ dwc3_imx->suspend_clk = devm_clk_get(dev, "suspend");
+ if (IS_ERR(dwc3_imx->suspend_clk)) {
+ err = PTR_ERR(dwc3_imx->suspend_clk);
+ dev_err(dev, "Failed to get suspend clk, err=%d\n", err);
+ goto disable_hsio_clk;
+ }
+
+ err = clk_prepare_enable(dwc3_imx->suspend_clk);
+ if (err) {
+ dev_err(dev, "Failed to enable suspend clk, err=%d\n", err);
+ goto disable_hsio_clk;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ err = irq;
+ goto disable_clks;
+ }
+ dwc3_imx->irq = irq;
+
+ err = devm_request_threaded_irq(dev, irq, NULL, dwc3_imx8mp_interrupt,
+ IRQF_ONESHOT, dev_name(dev), dwc3_imx);
+ if (err) {
+ dev_err(dev, "failed to request IRQ #%d --> %d\n", irq, err);
+ goto disable_clks;
+ }
+
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ err = pm_runtime_get_sync(dev);
+ if (err < 0)
+ goto disable_rpm;
+
+ dwc3_np = of_get_child_by_name(node, "dwc3");
+ if (!dwc3_np) {
+ dev_err(dev, "failed to find dwc3 core child\n");
+ goto disable_rpm;
+ }
+
+ err = of_platform_populate(node, NULL, NULL, dev);
+ if (err) {
+ dev_err(&pdev->dev, "failed to create dwc3 core\n");
+ goto err_node_put;
+ }
+
+ dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np);
+ if (!dwc3_imx->dwc3) {
+ dev_err(dev, "failed to get dwc3 platform device\n");
+ err = -ENODEV;
+ goto depopulate;
+ }
+ of_node_put(dwc3_np);
+
+ device_set_wakeup_capable(dev, true);
+ pm_runtime_put(dev);
+
+ return 0;
+
+depopulate:
+ of_platform_depopulate(dev);
+err_node_put:
+ of_node_put(dwc3_np);
+disable_rpm:
+ pm_runtime_disable(dev);
+ pm_runtime_put_noidle(dev);
+disable_clks:
+ clk_disable_unprepare(dwc3_imx->suspend_clk);
+disable_hsio_clk:
+ clk_disable_unprepare(dwc3_imx->hsio_clk);
+
+ return err;
+}
+
+static int dwc3_imx8mp_remove(struct platform_device *pdev)
+{
+ struct dwc3_imx8mp *dwc3_imx = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+
+ pm_runtime_get_sync(dev);
+ of_platform_depopulate(dev);
+
+ clk_disable_unprepare(dwc3_imx->suspend_clk);
+ clk_disable_unprepare(dwc3_imx->hsio_clk);
+
+ pm_runtime_disable(dev);
+ pm_runtime_put_noidle(dev);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_suspend(struct dwc3_imx8mp *dwc3_imx,
+ pm_message_t msg)
+{
+ if (dwc3_imx->pm_suspended)
+ return 0;
+
+ /* Wakeup enable */
+ if (PMSG_IS_AUTO(msg) || device_may_wakeup(dwc3_imx->dev))
+ dwc3_imx8mp_wakeup_enable(dwc3_imx);
+
+ dwc3_imx->pm_suspended = true;
+
+ return 0;
+}
+
+static int __maybe_unused dwc3_imx8mp_resume(struct dwc3_imx8mp *dwc3_imx,
+ pm_message_t msg)
+{
+ struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3);
+ int ret = 0;
+
+ if (!dwc3_imx->pm_suspended)
+ return 0;
+
+ /* Wakeup disable */
+ dwc3_imx8mp_wakeup_disable(dwc3_imx);
+ dwc3_imx->pm_suspended = false;
+
+ if (dwc3_imx->wakeup_pending) {
+ dwc3_imx->wakeup_pending = false;
+ if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) {
+ pm_runtime_mark_last_busy(dwc->dev);
+ pm_runtime_put_autosuspend(dwc->dev);
+ } else {
+ /*
+ * Add wait for xhci switch from suspend
+ * clock to normal clock to detect connection.
+ */
+ usleep_range(9000, 10000);
+ }
+ enable_irq(dwc3_imx->irq);
+ }
+
+ return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_suspend(struct device *dev)
+{
+ struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = dwc3_imx8mp_suspend(dwc3_imx, PMSG_SUSPEND);
+
+ if (device_may_wakeup(dwc3_imx->dev))
+ enable_irq_wake(dwc3_imx->irq);
+ else
+ clk_disable_unprepare(dwc3_imx->suspend_clk);
+
+ clk_disable_unprepare(dwc3_imx->hsio_clk);
+ dev_dbg(dev, "dwc3 imx8mp pm suspend.\n");
+
+ return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_pm_resume(struct device *dev)
+{
+ struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+ int ret;
+
+ if (device_may_wakeup(dwc3_imx->dev)) {
+ disable_irq_wake(dwc3_imx->irq);
+ } else {
+ ret = clk_prepare_enable(dwc3_imx->suspend_clk);
+ if (ret)
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dwc3_imx->hsio_clk);
+ if (ret)
+ return ret;
+
+ ret = dwc3_imx8mp_resume(dwc3_imx, PMSG_RESUME);
+
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ dev_dbg(dev, "dwc3 imx8mp pm resume.\n");
+
+ return ret;
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_suspend(struct device *dev)
+{
+ struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "dwc3 imx8mp runtime suspend.\n");
+
+ return dwc3_imx8mp_suspend(dwc3_imx, PMSG_AUTO_SUSPEND);
+}
+
+static int __maybe_unused dwc3_imx8mp_runtime_resume(struct device *dev)
+{
+ struct dwc3_imx8mp *dwc3_imx = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "dwc3 imx8mp runtime resume.\n");
+
+ return dwc3_imx8mp_resume(dwc3_imx, PMSG_AUTO_RESUME);
+}
+
+static const struct dev_pm_ops dwc3_imx8mp_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_imx8mp_pm_suspend, dwc3_imx8mp_pm_resume)
+ SET_RUNTIME_PM_OPS(dwc3_imx8mp_runtime_suspend,
+ dwc3_imx8mp_runtime_resume, NULL)
+};
+
+static const struct of_device_id dwc3_imx8mp_of_match[] = {
+ { .compatible = "fsl,imx8mp-dwc3", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, dwc3_imx8mp_of_match);
+
+static struct platform_driver dwc3_imx8mp_driver = {
+ .probe = dwc3_imx8mp_probe,
+ .remove = dwc3_imx8mp_remove,
+ .driver = {
+ .name = "imx8mp-dwc3",
+ .pm = &dwc3_imx8mp_dev_pm_ops,
+ .of_match_table = dwc3_imx8mp_of_match,
+ },
+};
+
+module_platform_driver(dwc3_imx8mp_driver);
+
+MODULE_ALIAS("platform:imx8mp-dwc3");
+MODULE_AUTHOR("jun.li@nxp.com");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 imx8mp Glue Layer");
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
` (3 preceding siblings ...)
2020-09-22 10:46 ` [PATCH v3 4/6] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
@ 2020-09-22 10:46 ` Li Jun
2020-09-22 14:39 ` Krzysztof Kozlowski
2020-09-23 7:50 ` Sascha Hauer
2020-09-22 10:46 ` [PATCH v3 6/6] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
5 siblings, 2 replies; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
imx8mp integrates 2 identical dwc3 based USB3 controllers and
Synopsys phys, each instance has additional wakeup logic to
support low power mode, so the glue layer need a node with dwc3
core sub node.
Signed-off-by: Li Jun <jun.li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9de2aa1..1b7ed4c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -750,5 +750,93 @@
reg = <0x3d800000 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ usb3_phy0: usb-phy@381f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x381f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_0: usb@32f10100 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10100 0x8>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_0: dwc3@38100000 {
+ compatible = "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis-u2-freeclk-exists-quirk;
+ xhci-64bit-support-disable;
+ status = "disabled";
+ };
+
+ };
+
+ usb3_phy1: usb-phy@382f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x382f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_1: usb@32f10108 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10108 0x8>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "hsio", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_1: dwc3@38200000 {
+ compatible = "snps,dwc3";
+ reg = <0x38200000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis-u2-freeclk-exists-quirk;
+ xhci-64bit-support-disable;
+ status = "disabled";
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/6] arm64: dts: imx8mp-evk: enable usb1 as host mode
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
` (4 preceding siblings ...)
2020-09-22 10:46 ` [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes Li Jun
@ 2020-09-22 10:46 ` Li Jun
5 siblings, 0 replies; 15+ messages in thread
From: Li Jun @ 2020-09-22 10:46 UTC (permalink / raw)
To: robh+dt, shawnguo, balbi, mathias.nyman
Cc: gregkh, s.hauer, kernel, festevam, linux-imx, Anson.Huang,
jun.li, aisheng.dong, peng.fan, fugang.duan, qiangqing.zhang,
horia.geanta, linux-usb, devicetree, linux-arm-kernel
Enable usb host port with type-A connector on imx8mp-evk board.
Signed-off-by: Li Jun <jun.li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 432c1a7..0cb3b16 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -176,6 +176,21 @@
};
};
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@@ -276,6 +291,12 @@
>;
};
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR 0x19
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
--
2.7.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
2020-09-22 10:46 ` [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
@ 2020-09-22 14:32 ` Krzysztof Kozlowski
2020-09-22 16:45 ` Jun Li
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2020-09-22 14:32 UTC (permalink / raw)
To: Li Jun
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, aisheng.dong, peng.fan,
fugang.duan, qiangqing.zhang, horia.geanta, linux-usb,
devicetree, linux-arm-kernel
On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote:
>
> NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic
> to support low power mode, the glue layer is for this wakeup
> functionality, which has a separated interrupt, can support
> wakeup from U3 and connect events for host, and vbus wakeup for
> device.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
> .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99 ++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> new file mode 100644
> index 0000000..a5d5566
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP iMX8MP Soc USB Controller
> +
> +maintainers:
> + - Li Jun <jun.li@nxp.com>
> +
> +properties:
> + compatible:
> + items:
Items are not necessary
> + - const: fsl,imx8mp-dwc3
> +
> + reg:
> + maxItems: 1
> + description: Address and length of the register set for the wrapper of
> + dwc3 core on the SOC.
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + ranges: true
> +
> + interrupts:
> + maxItems: 1
> + description: The interrupt that is asserted when a wakeup event is
> + received.
> +
> + clocks:
> + description:
> + A list of phandle and clock-specifier pairs for the clocks
> + listed in clock-names.
> + items:
> + - description: system hsio root clock.
> + - description: suspend clock, used for usb wakeup logic.
> +
> + clock-names:
> + items:
> + - const: hsio
> + - const: suspend
> +
> +# Required child node:
> +
> +patternProperties:
> + "^dwc3@[0-9a-f]+$":
> + type: object
> + description:
> + A child node must exist to represent the core DWC3 IP block
> + The content of the node is defined in dwc3.txt.
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> + - clocks
> + - clock-names
> + - interrupts
> +
> +additionalProperties: false
Do you actually validate your DTS changes with this schema? They do
not look like passing the validation...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes
2020-09-22 10:46 ` [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes Li Jun
@ 2020-09-22 14:39 ` Krzysztof Kozlowski
2020-09-23 7:50 ` Sascha Hauer
1 sibling, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2020-09-22 14:39 UTC (permalink / raw)
To: Li Jun
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, aisheng.dong, peng.fan,
fugang.duan, qiangqing.zhang, horia.geanta, linux-usb,
devicetree, linux-arm-kernel
On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote:
>
> imx8mp integrates 2 identical dwc3 based USB3 controllers and
> Synopsys phys, each instance has additional wakeup logic to
> support low power mode, so the glue layer need a node with dwc3
> core sub node.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 9de2aa1..1b7ed4c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -750,5 +750,93 @@
> reg = <0x3d800000 0x400000>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + usb3_phy0: usb-phy@381f0040 {
> + compatible = "fsl,imx8mp-usb-phy";
> + reg = <0x381f0040 0x40>;
> + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> + clock-names = "phy";
> + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usb3_0: usb@32f10100 {
> + compatible = "fsl,imx8mp-dwc3";
> + reg = <0x32f10100 0x8>;
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_USB_ROOT>;
> + clock-names = "hsio", "suspend";
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + usb_dwc3_0: dwc3@38100000 {
> + compatible = "snps,dwc3";
> + reg = <0x38100000 0x10000>;
> + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_USB_CORE_REF>,
> + <&clk IMX8MP_CLK_USB_ROOT>;
> + clock-names = "bus_early", "ref", "suspend";
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&usb3_phy0>, <&usb3_phy0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + snps,dis-u2-freeclk-exists-quirk;
> + xhci-64bit-support-disable;
> + status = "disabled";
> + };
> +
> + };
> +
> + usb3_phy1: usb-phy@382f0040 {
> + compatible = "fsl,imx8mp-usb-phy";
> + reg = <0x382f0040 0x40>;
> + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> + clock-names = "phy";
> + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> + assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usb3_1: usb@32f10108 {
> + compatible = "fsl,imx8mp-dwc3";
> + reg = <0x32f10108 0x8>;
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_USB_ROOT>;
> + clock-names = "hsio", "suspend";
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
This does not validate against your own schema:
arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml: usb@32f10108:
'assigned-clock-parents', 'assigned-clock-rates', 'assigned-clocks' do
not match any of the regexes: '^dwc3@[0-9a-f]+$', 'pinctrl-[0-9]+'
Please, stop adding new schema and DTS which from day one have
warnings/violations.
It's really a lot of effort (and commits) to clean this up later.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
2020-09-22 14:32 ` Krzysztof Kozlowski
@ 2020-09-22 16:45 ` Jun Li
2020-09-22 18:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 15+ messages in thread
From: Jun Li @ 2020-09-22 16:45 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, dl-linux-imx, Anson Huang, Aisheng Dong, Peng Fan,
Andy Duan, Joakim Zhang, Horia Geanta, linux-usb, devicetree,
linux-arm-kernel
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, September 22, 2020 10:33 PM
> To: Jun Li <jun.li@nxp.com>
> Cc: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org;
> mathias.nyman@intel.com; gregkh@linuxfoundation.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> dl-linux-imx <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>;
> Aisheng Dong <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3
> glue bindings
>
> On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote:
> >
> > NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic to
> > support low power mode, the glue layer is for this wakeup
> > functionality, which has a separated interrupt, can support wakeup
> > from U3 and connect events for host, and vbus wakeup for device.
> >
> > Signed-off-by: Li Jun <jun.li@nxp.com>
> > ---
> > .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99
> ++++++++++++++++++++++
> > 1 file changed, 99 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > new file mode 100644
> > index 0000000..a5d5566
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > @@ -0,0 +1,99 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright
> > +(c) 2020 NXP %YAML 1.2
> > +---
> > +$id:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fusb%2Ffsl%2Cimx8mp-dwc3.yaml%23&data=02%7C
> >
> +01%7Cjun.li%40nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc
> >
> +2b4c6fa92cd99c5c301635%7C0%7C0%7C637363819819667936&sdata=IvFQ8l0
> > +7VXUMbG8riyITSTZb1P50oIXs%2BkAV%2FeX8ntk%3D&reserved=0
> > +$schema:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=02%7C01%7Cjun.li%40
> >
> +nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc2b4c6fa92cd99c
> >
> +5c301635%7C0%7C0%7C637363819819677934&sdata=H3%2BcwgiLKBynHv4N%2F
> > +dogBi3SwaizVHmqieJXVrErv0I%3D&reserved=0
> > +
> > +title: NXP iMX8MP Soc USB Controller
> > +
> > +maintainers:
> > + - Li Jun <jun.li@nxp.com>
> > +
> > +properties:
> > + compatible:
> > + items:
>
> Items are not necessary
>
>
> > + - const: fsl,imx8mp-dwc3
> > +
> > + reg:
> > + maxItems: 1
> > + description: Address and length of the register set for the wrapper
> of
> > + dwc3 core on the SOC.
> > +
> > + "#address-cells":
> > + enum: [ 1, 2 ]
> > +
> > + "#size-cells":
> > + enum: [ 1, 2 ]
> > +
> > + ranges: true
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: The interrupt that is asserted when a wakeup event is
> > + received.
> > +
> > + clocks:
> > + description:
> > + A list of phandle and clock-specifier pairs for the clocks
> > + listed in clock-names.
> > + items:
> > + - description: system hsio root clock.
> > + - description: suspend clock, used for usb wakeup logic.
> > +
> > + clock-names:
> > + items:
> > + - const: hsio
> > + - const: suspend
> > +
> > +# Required child node:
> > +
> > +patternProperties:
> > + "^dwc3@[0-9a-f]+$":
> > + type: object
> > + description:
> > + A child node must exist to represent the core DWC3 IP block
> > + The content of the node is defined in dwc3.txt.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - ranges
> > + - clocks
> > + - clock-names
> > + - interrupts
> > +
> > +additionalProperties: false
>
> Do you actually validate your DTS changes with this schema? They do not look
> like passing the validation...
I did run dt_binding_check, maybe I missed some errors as there are always some other
failures, I will re-run to double check.
Li Jun
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings
2020-09-22 16:45 ` Jun Li
@ 2020-09-22 18:22 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2020-09-22 18:22 UTC (permalink / raw)
To: Jun Li
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, dl-linux-imx, Anson Huang, Aisheng Dong, Peng Fan,
Andy Duan, Joakim Zhang, Horia Geanta, linux-usb, devicetree,
linux-arm-kernel
On Tue, 22 Sep 2020 at 18:45, Jun Li <jun.li@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzk@kernel.org>
> > Sent: Tuesday, September 22, 2020 10:33 PM
> > To: Jun Li <jun.li@nxp.com>
> > Cc: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org;
> > mathias.nyman@intel.com; gregkh@linuxfoundation.org;
> > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> > dl-linux-imx <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>;
> > Aisheng Dong <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> > <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia
> > Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> > Subject: Re: [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3
> > glue bindings
> >
> > On Tue, 22 Sep 2020 at 12:56, Li Jun <jun.li@nxp.com> wrote:
> > >
> > > NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic to
> > > support low power mode, the glue layer is for this wakeup
> > > functionality, which has a separated interrupt, can support wakeup
> > > from U3 and connect events for host, and vbus wakeup for device.
> > >
> > > Signed-off-by: Li Jun <jun.li@nxp.com>
> > > ---
> > > .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 99
> > ++++++++++++++++++++++
> > > 1 file changed, 99 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > > b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > > new file mode 100644
> > > index 0000000..a5d5566
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
> > > @@ -0,0 +1,99 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright
> > > +(c) 2020 NXP %YAML 1.2
> > > +---
> > > +$id:
> > >
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > >
> > +cetree.org%2Fschemas%2Fusb%2Ffsl%2Cimx8mp-dwc3.yaml%23&data=02%7C
> > >
> > +01%7Cjun.li%40nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc
> > >
> > +2b4c6fa92cd99c5c301635%7C0%7C0%7C637363819819667936&sdata=IvFQ8l0
> > > +7VXUMbG8riyITSTZb1P50oIXs%2BkAV%2FeX8ntk%3D&reserved=0
> > > +$schema:
> > >
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > >
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=02%7C01%7Cjun.li%40
> > >
> > +nxp.com%7Ceaedeb64ec15472183d108d85f046841%7C686ea1d3bc2b4c6fa92cd99c
> > >
> > +5c301635%7C0%7C0%7C637363819819677934&sdata=H3%2BcwgiLKBynHv4N%2F
> > > +dogBi3SwaizVHmqieJXVrErv0I%3D&reserved=0
> > > +
> > > +title: NXP iMX8MP Soc USB Controller
> > > +
> > > +maintainers:
> > > + - Li Jun <jun.li@nxp.com>
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> >
> > Items are not necessary
> >
> >
> > > + - const: fsl,imx8mp-dwc3
> > > +
> > > + reg:
> > > + maxItems: 1
> > > + description: Address and length of the register set for the wrapper
> > of
> > > + dwc3 core on the SOC.
> > > +
> > > + "#address-cells":
> > > + enum: [ 1, 2 ]
> > > +
> > > + "#size-cells":
> > > + enum: [ 1, 2 ]
> > > +
> > > + ranges: true
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > + description: The interrupt that is asserted when a wakeup event is
> > > + received.
> > > +
> > > + clocks:
> > > + description:
> > > + A list of phandle and clock-specifier pairs for the clocks
> > > + listed in clock-names.
> > > + items:
> > > + - description: system hsio root clock.
> > > + - description: suspend clock, used for usb wakeup logic.
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: hsio
> > > + - const: suspend
> > > +
> > > +# Required child node:
> > > +
> > > +patternProperties:
> > > + "^dwc3@[0-9a-f]+$":
> > > + type: object
> > > + description:
> > > + A child node must exist to represent the core DWC3 IP block
> > > + The content of the node is defined in dwc3.txt.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - "#address-cells"
> > > + - "#size-cells"
> > > + - ranges
> > > + - clocks
> > > + - clock-names
> > > + - interrupts
> > > +
> > > +additionalProperties: false
> >
> > Do you actually validate your DTS changes with this schema? They do not look
> > like passing the validation...
>
> I did run dt_binding_check, maybe I missed some errors as there are always some other
> failures, I will re-run to double check.
dt_binding_check is good for the binding and example. Except this you
need to run dtbs_check so your new DTS will be checked. In this case
it points to missing properties in the bindings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes
2020-09-22 10:46 ` [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes Li Jun
2020-09-22 14:39 ` Krzysztof Kozlowski
@ 2020-09-23 7:50 ` Sascha Hauer
2020-09-23 8:49 ` Jun Li
1 sibling, 1 reply; 15+ messages in thread
From: Sascha Hauer @ 2020-09-23 7:50 UTC (permalink / raw)
To: Li Jun
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, kernel,
festevam, linux-imx, Anson.Huang, aisheng.dong, peng.fan,
fugang.duan, qiangqing.zhang, horia.geanta, linux-usb,
devicetree, linux-arm-kernel
On Tue, Sep 22, 2020 at 06:46:51PM +0800, Li Jun wrote:
> imx8mp integrates 2 identical dwc3 based USB3 controllers and
> Synopsys phys, each instance has additional wakeup logic to
> support low power mode, so the glue layer need a node with dwc3
> core sub node.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88 +++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 9de2aa1..1b7ed4c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> + usb3_1: usb@32f10108 {
> + compatible = "fsl,imx8mp-dwc3";
> + reg = <0x32f10108 0x8>;
> + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> + <&clk IMX8MP_CLK_USB_ROOT>;
> + clock-names = "hsio", "suspend";
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
In Linux-5.9-rc6 this clock doesn't exist anymore. Should be
IMX8MP_CLK_HSIO_AXI
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + usb_dwc3_1: dwc3@38200000 {
> + compatible = "snps,dwc3";
> + reg = <0x38200000 0x10000>;
> + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_USB_CORE_REF>,
> + <&clk IMX8MP_CLK_USB_ROOT>;
> + clock-names = "bus_early", "ref", "suspend";
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&usb3_phy1>, <&usb3_phy1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + snps,dis-u2-freeclk-exists-quirk;
> + xhci-64bit-support-disable;
> + status = "disabled";
Does it make sense for a board to enable the parent node and leave this
one disabled? If not you can drop this status = "disabled" here.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes
2020-09-23 7:50 ` Sascha Hauer
@ 2020-09-23 8:49 ` Jun Li
0 siblings, 0 replies; 15+ messages in thread
From: Jun Li @ 2020-09-23 8:49 UTC (permalink / raw)
To: Sascha Hauer
Cc: robh+dt, shawnguo, balbi, mathias.nyman, gregkh, kernel,
festevam, dl-linux-imx, Anson Huang, Aisheng Dong, Peng Fan,
Andy Duan, Joakim Zhang, Horia Geanta, linux-usb, devicetree,
linux-arm-kernel
> -----Original Message-----
> From: Sascha Hauer <s.hauer@pengutronix.de>
> Sent: Wednesday, September 23, 2020 3:51 PM
> To: Jun Li <jun.li@nxp.com>
> Cc: robh+dt@kernel.org; shawnguo@kernel.org; balbi@kernel.org;
> mathias.nyman@intel.com; gregkh@linuxfoundation.org;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes
>
> On Tue, Sep 22, 2020 at 06:46:51PM +0800, Li Jun wrote:
> > imx8mp integrates 2 identical dwc3 based USB3 controllers and Synopsys
> > phys, each instance has additional wakeup logic to support low power
> > mode, so the glue layer need a node with dwc3 core sub node.
> >
> > Signed-off-by: Li Jun <jun.li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 88
> > +++++++++++++++++++++++++++++++
> > 1 file changed, 88 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 9de2aa1..1b7ed4c 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > + usb3_1: usb@32f10108 {
> > + compatible = "fsl,imx8mp-dwc3";
> > + reg = <0x32f10108 0x8>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> > + <&clk IMX8MP_CLK_USB_ROOT>;
> > + clock-names = "hsio", "suspend";
> > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
>
> In Linux-5.9-rc6 this clock doesn't exist anymore. Should be
> IMX8MP_CLK_HSIO_AXI
Will change.
>
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > + status = "disabled";
> > +
> > + usb_dwc3_1: dwc3@38200000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x38200000 0x10000>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > + <&clk IMX8MP_CLK_USB_CORE_REF>,
> > + <&clk IMX8MP_CLK_USB_ROOT>;
> > + clock-names = "bus_early", "ref", "suspend";
> > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&usb3_phy1>, <&usb3_phy1>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + snps,dis-u2-freeclk-exists-quirk;
> > + xhci-64bit-support-disable;
> > + status = "disabled";
>
> Does it make sense for a board to enable the parent node and leave this one
> disabled? If not you can drop this status = "disabled" here.
OK, will drop it.
Thanks
Li Jun
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 |
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pe
> ngutronix.de%2F&data=02%7C01%7Cjun.li%40nxp.com%7Cadbbbfe2edec4cca1
> 38908d85f956382%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6373644425
> 20571896&sdata=07ku8kTQCv8lv8qdRiOcU3CX4lly3503LO4bUDIbjow%3D&r
> eserved=0 |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support
2020-09-22 10:46 ` [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support Li Jun
@ 2020-09-29 18:11 ` Rob Herring
2020-10-02 16:39 ` Jun Li
0 siblings, 1 reply; 15+ messages in thread
From: Rob Herring @ 2020-09-29 18:11 UTC (permalink / raw)
To: Li Jun
Cc: shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, linux-imx, Anson.Huang, aisheng.dong, peng.fan,
fugang.duan, qiangqing.zhang, horia.geanta, linux-usb,
devicetree, linux-arm-kernel
On Tue, Sep 22, 2020 at 06:46:47PM +0800, Li Jun wrote:
> Add a property "xhci-64bit-support-disable" to disable xhci 64bit address
> dma, some SoC integration may not support 64bit DMA but the AC64 bit
> (bit 0) of HCCPARAMS1 is kept to be 1.
Use 'dma-ranges' for this.
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
> Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> index 0c5cff8..26446fb 100644
> --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> @@ -28,6 +28,9 @@ Optional properties:
> - quirk-broken-port-ped: set if the controller has broken port disable mechanism
> - imod-interval-ns: default interrupt moderation interval is 5000ns
> - phys : see usb-hcd.yaml in the current directory
> + - xhci-64bit-support-disable: set if the AC64 bit (bit 0) of HCCPARAMS1 is
> + set to be 1, but the controller actually can't handle 64-bit address
> + due to SoC integration.
>
> additionally the properties from usb-hcd.yaml (in the current directory) are
> supported.
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support
2020-09-29 18:11 ` Rob Herring
@ 2020-10-02 16:39 ` Jun Li
0 siblings, 0 replies; 15+ messages in thread
From: Jun Li @ 2020-10-02 16:39 UTC (permalink / raw)
To: Rob Herring
Cc: shawnguo, balbi, mathias.nyman, gregkh, s.hauer, kernel,
festevam, dl-linux-imx, Anson Huang, Aisheng Dong, Peng Fan,
Andy Duan, Joakim Zhang, Horia Geanta, linux-usb, devicetree,
linux-arm-kernel
Hi Rob,
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, September 30, 2020 2:11 AM
> To: Jun Li <jun.li@nxp.com>
> Cc: shawnguo@kernel.org; balbi@kernel.org; mathias.nyman@intel.com;
> gregkh@linuxfoundation.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Anson Huang <anson.huang@nxp.com>; Aisheng Dong
> <aisheng.dong@nxp.com>; Peng Fan <peng.fan@nxp.com>; Andy Duan
> <fugang.duan@nxp.com>; Joakim Zhang <qiangqing.zhang@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable
> xhci 64bit support
>
> On Tue, Sep 22, 2020 at 06:46:47PM +0800, Li Jun wrote:
> > Add a property "xhci-64bit-support-disable" to disable xhci 64bit
> > address dma, some SoC integration may not support 64bit DMA but the
> > AC64 bit (bit 0) of HCCPARAMS1 is kept to be 1.
>
> Use 'dma-ranges' for this.
Thanks, sent out v4 with dma-ranges property approach.
Li Jun
>
> > Signed-off-by: Li Jun <jun.li@nxp.com>
> > ---
> > Documentation/devicetree/bindings/usb/usb-xhci.txt | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > index 0c5cff8..26446fb 100644
> > --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> > @@ -28,6 +28,9 @@ Optional properties:
> > - quirk-broken-port-ped: set if the controller has broken port disable
> mechanism
> > - imod-interval-ns: default interrupt moderation interval is 5000ns
> > - phys : see usb-hcd.yaml in the current directory
> > + - xhci-64bit-support-disable: set if the AC64 bit (bit 0) of HCCPARAMS1
> is
> > + set to be 1, but the controller actually can't handle 64-bit address
> > + due to SoC integration.
> >
> > additionally the properties from usb-hcd.yaml (in the current
> > directory) are supported.
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-10-02 16:39 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-22 10:46 [PATCH v3 0/6] add NXP imx8mp usb support Li Jun
2020-09-22 10:46 ` [PATCH v3 1/6] dt-bindings: usb: xhci: add property to disable xhci 64bit support Li Jun
2020-09-29 18:11 ` Rob Herring
2020-10-02 16:39 ` Jun Li
2020-09-22 10:46 ` [PATCH v3 2/6] usb: host: xhci-plat: add support of XHCI_NO_64BIT_SUPPORT via property Li Jun
2020-09-22 10:46 ` [PATCH v3 3/6] dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings Li Jun
2020-09-22 14:32 ` Krzysztof Kozlowski
2020-09-22 16:45 ` Jun Li
2020-09-22 18:22 ` Krzysztof Kozlowski
2020-09-22 10:46 ` [PATCH v3 4/6] usb: dwc3: add imx8mp dwc3 glue layer driver Li Jun
2020-09-22 10:46 ` [PATCH v3 5/6] arm64: dtsi: imx8mp: add usb nodes Li Jun
2020-09-22 14:39 ` Krzysztof Kozlowski
2020-09-23 7:50 ` Sascha Hauer
2020-09-23 8:49 ` Jun Li
2020-09-22 10:46 ` [PATCH v3 6/6] arm64: dts: imx8mp-evk: enable usb1 as host mode Li Jun
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