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x-microsoft-antispam-message-info: iI26YW65zwYRzPoIYs1OYz6Y9ms3TVq/VoCTqd2EK1oYAeQod4NrSTXAwWfrwMAcg3ODUYKWZ8VH5BBZP4rDfswiIbgAConN9AHQ7xUycm5wvlZsl002HmF2hNDAxNBtf0eyMMZ0ldREjQ5eIC764NVAXM59R08k0OVHroUXAWNyfXvKhFCLtXaDRzPFuIJkKLjSGCn2/34KPDyF/AWExXFs2Irlb1OaWvpXn0Pd/Mu63h5Td8+7FR/Q4TCipR2ER7uABBAq9AaJeRR1vlEKWjaIvH917Edf0tMdUQFTWIIQgyA3AyNbtyYu6g6d01XH138tLMhOdoB8OZUuyOecop/gJ9nBkJON1GMwtWw6KOvQzmPwSwEea5b+vtgBTnueelZG89SboGHWH6tIsxTRtUpItYYZBFYzpSDd3a5NcI8Jry71n0LUY5KWGBSqitao x-ms-exchange-antispam-messagedata: zS5vrQc5fImSKo+nx+475cKzcgx+H32IAOulu1use/Ev53VAVAwyZzodJ3YRIrOFZ30u9p6760YIuieH/nhjt1qkxO3wPLfGVRL7gSzskgZOCE2n3bsGKCWTQZVOgRsDcXTfzDVZBOv6XelcYHAyVw== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f30710f7-919f-4c17-9393-08d7b0914538 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Feb 2020 14:30:27.2395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9ya4YXurObMjzvYNJAjBBlakZJYMDrSJYxzsE61kTWKzowRXllwL5nUNQGG837aSOvi1MnE8/sDkTOxA//rOTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5597 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 13.02.2020 13:32, Lucas Stach wrote:=0A= > On Do, 2020-02-13 at 09:21 +0000, Jacky Bai wrote:=0A= >>> -----Original Message-----=0A= >>> From: Schrempf Frieder =0A= >>> Sent: Thursday, February 13, 2020 5:16 PM=0A= >>> To: Adam Ford ; Sudeep Holla=0A= >>> =0A= >>> Cc: Aisheng Dong ; mark.rutland@arm.com; Peng=0A= >>> Fan ; Souvik Chakravarty=0A= >>> ; Jacky Bai ;=0A= >>> devicetree@vger.kernel.org; Cl=E9ment Faure ;=0A= >>> s.hauer@pengutronix.de; shawnguo@kernel.org; robh+dt@kernel.org;=0A= >>> dl-linux-imx ; kernel@pengutronix.de; Andre Przywara= =0A= >>> ; Silvano Di Ninno ;= =0A= >>> Leonard Crestez ; festevam@gmail.com;=0A= >>> linux-arm-kernel@lists.infradead.org; Lucas Stach =0A= >>> Subject: Re: [PATCH 0/3] Add power domain driver support for i.mx8m fam= ily=0A= >>>=0A= >>> Hi,=0A= >>>=0A= >>> On 07.11.19 22:28, Adam Ford wrote:=0A= >>>> On Thu, Apr 18, 2019 at 9:43 AM Sudeep Holla =0A= >>> wrote:=0A= >>>>> On Wed, Apr 17, 2019 at 04:21:55PM +0000, Leonard Crestez wrote:=0A= >>>>>> On 4/17/2019 4:33 PM, Sudeep Holla wrote:=0A= >>>>>>>>> I don't yet buy the security argument. There are many more shared= =0A= >>>>>>>>> parts on the SoC, like the clock controller, that would need to= =0A= >>>>>>>>> be taken away from the non-secure world if one would want to run= =0A= >>>>>>>>> an untrusted OS kernel on a i.MX8M system.=0A= >>>>>>>>>=0A= >>>>>>>>> To properly implement security on any i.MX8M based system the=0A= >>>>>>>>> firmware would need to grow something like a full ARM SCPI=0A= >>>>>>>>> implementation, so all shared critical peripherals are solely und= er=0A= >>> firmware control.=0A= >>>>>>>> It might be possible to rework this to use some form of=0A= >>>>>>>> SCMI-over-SMC instead of vendor-specific SMCCC SIP calls=0A= >>>>=0A= >>>> I was just curious to know if there is any progress being made on=0A= >>>> this. The i.mx8mm-evk is missing functionality upstream and I think= =0A= >>>> the power domain support would help enable some of these features.=0A= >>>>=0A= >>>=0A= >>> Has there been any decision or action taken in this topic?=0A= >>> Will the power domain driver as proposed in this patch be upstreamed at= =0A= >>> some time, or rather not?=0A= >>>=0A= >>> I try to build a mainline BSP for i.MX8MM (ML U-Boot, ML TF-A, ML Linux= )=0A= >>> and I integrated display and graphics support from the downstream NXP= =0A= >>> kernel.=0A= >>>=0A= >>> While most things already work fine, there's the issue of how to handle= the=0A= >>> power domains. Currently I need to ungate some clocks in the TF-A=0A= >>> BL31 to get for example the GPU running. If I understand this correctly= the=0A= >>> proposed power domain driver could handle this in Linux otherwise.=0A= >>>=0A= >>=0A= >> the SCMI over SMC is still under review=0A= > =0A= > Even if the SCMI over SMC is ready at some point, it's still unclear to= =0A= > me how you intend to abstract the GPC behind the SCMI interface in the=0A= > TF-A. The power domains have dependencies both into the regulator and=0A= > the clock framework. Both are currently under exclusive control of the=0A= > rich OS. How do you intend to allow the TF-A to control the power=0A= > supplies and necessary reset clocks without messing up any state in the= =0A= > rich OS?=0A= =0A= This is indeed difficult, SCMI assumes that the responder has sufficient = =0A= control over clocks to fully implement power domain handling, including =0A= over clocks and regulators.=0A= =0A= Perhaps it might be possible to modify current gpcv2 driver to send SCMI = =0A= messages for power only and keep handling regulators itself? It could =0A= switch based on whether it has a reference to a scmi channel as a DT =0A= property.=0A= =0A= A full scmi-based implementation might use entirely very different =0A= bindings and take a long time. If people want to support their chips by =0A= implementing power domain support in the rich OS we shouldn't block them.= =0A= =0A= So it would be good to accept gpcv2 enhancement for 8mm and similar.=0A= =0A= --=0A= Regards,=0A= Leonard=0A=