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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u22sm1640614oie.26.2021.07.09.21.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 21:17:26 -0700 (PDT) Date: Fri, 9 Jul 2021 23:17:24 -0500 From: Bjorn Andersson To: Thara Gopinath Cc: agross@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org, tdas@codeaurora.org, mka@chromium.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [Patch v3 4/6] arm64: boot: dts: qcom: sdm45: Add support for LMh node Message-ID: References: <20210708120656.663851-1-thara.gopinath@linaro.org> <20210708120656.663851-5-thara.gopinath@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210708120656.663851-5-thara.gopinath@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 08 Jul 07:06 CDT 2021, Thara Gopinath wrote: > Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt > support in cpufreq node to capture the LMh interrupt and let the scheduler > know of the max frequency throttling. > Reviewed-by: Bjorn Andersson Regards, Bjorn > Signed-off-by: Thara Gopinath > --- > > v2->v3: > - Changed the LMh low and high trip to 94500 and 95000 mC from > 74500 and 75000 mC. This was a bug that got introduced in v2. > v1->v2: > - Dropped dt property qcom,support-lmh as per Bjorn's review comments. > - Changed lmh compatible from generic to platform specific. > - Introduced properties specifying arm, low and high temp thresholds for LMh > as per Daniel's suggestion. > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0a86fe71a66d..4da6b8f3dd7b 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -3646,6 +3646,30 @@ swm: swm@c85 { > }; > }; > > + lmh_cluster1: lmh@17d70800 { > + compatible = "qcom,sdm845-lmh"; > + reg = <0 0x17d70800 0 0x401>; > + interrupts = ; > + qcom,lmh-cpu-id = <0x4>; > + qcom,lmh-temperature-arm = <65000>; > + qcom,lmh-temperature-low = <94500>; > + qcom,lmh-temperature-high = <95000>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + lmh_cluster0: lmh@17d78800 { > + compatible = "qcom,sdm845-lmh"; > + reg = <0 0x17d78800 0 0x401>; > + interrupts = ; > + qcom,lmh-cpu-id = <0x0>; > + qcom,lmh-temperature-arm = <65000>; > + qcom,lmh-temperature-low = <94500>; > + qcom,lmh-temperature-high = <95000>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > sound: sound { > }; > > @@ -4911,6 +4935,8 @@ cpufreq_hw: cpufreq@17d43000 { > reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; > reg-names = "freq-domain0", "freq-domain1"; > > + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; > + > clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; > clock-names = "xo", "alternate"; > > -- > 2.25.1 >