From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Thara Gopinath <thara.gopinath@linaro.org>
Cc: agross@kernel.org, rui.zhang@intel.com,
daniel.lezcano@linaro.org, viresh.kumar@linaro.org,
rjw@rjwysocki.net, robh+dt@kernel.org, tdas@codeaurora.org,
mka@chromium.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [Patch v3 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh
Date: Fri, 9 Jul 2021 23:21:29 -0500 [thread overview]
Message-ID: <YOkgSP5e3JaGY19V@yoga> (raw)
In-Reply-To: <20210708120656.663851-7-thara.gopinath@linaro.org>
On Thu 08 Jul 07:06 CDT 2021, Thara Gopinath wrote:
> Add dt binding documentation to describe Qualcomm
> Limits Management Hardware node.
>
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
> .../devicetree/bindings/thermal/qcom-lmh.yaml | 100 ++++++++++++++++++
> 1 file changed, 100 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> new file mode 100644
> index 000000000000..7f62bd3d543d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Limits Management Hardware(LMh)
> +
> +maintainers:
> + - Thara Gopinath <thara.gopinath@linaro.org>
> +
> +description:
> + Limits Management Hardware(LMh) is a hardware infrastructure on some
> + Qualcomm SoCs that can enforce temperature and current limits as
> + programmed by software for certain IPs like CPU.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sdm845-lmh
> +
> + reg:
> + items:
> + - description: core registers
> +
> + interrupts:
> + maxItems: 1
> +
> + '#interrupt-cells':
> + const: 1
> +
> + interrupt-controller: true
> +
> + qcom,lmh-cpu-id:
> + description:
> + CPU id of the first cpu in the LMh cluster
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + qcom,lmh-temperature-arm:
> + description:
> + An integer expressing temperature threshold in millicelsius at which
> + the LMh thermal FSM is engaged.
Do we know (by any public source) what "arm", "low" and "high" means
beyond that they somehow pokes the state machine?
> + $ref: /schemas/types.yaml#/definitions/int32
> +
> + qcom,lmh-temperature-low:
> + description:
> + An integer expressing temperature threshold in millicelsius at which
> + the LMh thermal FSM is engaged.
> + $ref: /schemas/types.yaml#/definitions/int32
> +
> + qcom,lmh-temperature-high:
> + description:
> + An integer expressing temperature threshold in millicelsius at which
> + the LMh thermal FSM is engaged.
> + $ref: /schemas/types.yaml#/definitions/int32
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - #interrupt-cells
> + - interrupt-controller
> + - qcom,lmh-cpu-id
> + - qcom,lmh-temperature-arm
> + - qcom,lmh-temperature-low
> + - qcom,lmh-temperature-high
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
I don't see why you need qcom,rpmh.h or the interconnect include in this
example.
> +
> + lmh_cluster1: lmh@17d70800 {
> + compatible = "qcom,sdm845-lmh";
> + reg = <0 0x17d70800 0 0x401>;
#address- and #size-cells are 1 in the wrapper that validates the
examples, so drop the two zeros.
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,lmh-cpu-id = <0x4>;
> + qcom,lmh-temperature-arm = <65000>;
> + qcom,lmh-temperature-low = <94500>;
> + qcom,lmh-temperature-high = <95000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + - |
This is a different example from the one above, if you intended that,
don't you need the #include of arm-gic.h here as well?
Regards,
Bjorn
> + lmh_cluster0: lmh@17d78800 {
> + compatible = "qcom,sdm845-lmh";
> + reg = <0 0x17d78800 0 0x401>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,lmh-cpu-id = <0x0>;
> + qcom,lmh-temperature-arm = <65000>;
> + qcom,lmh-temperature-low = <94500>;
> + qcom,lmh-temperature-high = <95000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + - |
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-07-10 4:21 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-08 12:06 [Patch v3 0/6] Introduce LMh driver for Qualcomm SoCs Thara Gopinath
2021-07-08 12:06 ` [Patch v3 1/6] firmware: qcom_scm: Introduce SCM calls to access LMh Thara Gopinath
2021-07-10 4:02 ` Bjorn Andersson
2021-07-08 12:06 ` [Patch v3 2/6] thermal: qcom: Add support for LMh driver Thara Gopinath
2021-07-10 4:15 ` Bjorn Andersson
2021-07-13 0:49 ` Thara Gopinath
2021-07-08 12:06 ` [Patch v3 3/6] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Thara Gopinath
2021-07-09 6:46 ` Viresh Kumar
2021-07-09 15:37 ` Thara Gopinath
2021-07-12 4:35 ` Viresh Kumar
2021-07-12 4:41 ` Viresh Kumar
2021-07-13 1:18 ` Thara Gopinath
2021-07-13 3:18 ` Viresh Kumar
2021-07-14 12:37 ` Thara Gopinath
2021-07-10 4:57 ` Bjorn Andersson
2021-07-13 1:09 ` Thara Gopinath
2021-07-08 12:06 ` [Patch v3 4/6] arm64: boot: dts: qcom: sdm45: Add support for LMh node Thara Gopinath
2021-07-10 4:17 ` Bjorn Andersson
2021-07-19 16:33 ` Bjorn Andersson
2021-07-19 22:44 ` Thara Gopinath
2021-07-08 12:06 ` [Patch v3 5/6] arm64: boot: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones Thara Gopinath
2021-07-10 4:17 ` Bjorn Andersson
2021-07-08 12:06 ` [Patch v3 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh Thara Gopinath
2021-07-10 4:21 ` Bjorn Andersson [this message]
2021-07-13 0:54 ` Thara Gopinath
2021-07-12 17:32 ` Rob Herring
2021-07-22 3:14 ` [Patch v3 0/6] Introduce LMh driver for Qualcomm SoCs Steev Klimaszewski
2021-07-27 15:29 ` Thara Gopinath
2021-07-27 17:43 ` Steev Klimaszewski
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