From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4803DC4363A for ; Fri, 23 Oct 2020 14:10:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F04BA208C3 for ; Fri, 23 Oct 2020 14:10:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S373946AbgJWOK3 (ORCPT ); Fri, 23 Oct 2020 10:10:29 -0400 Received: from foss.arm.com ([217.140.110.172]:53570 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S368882AbgJWOK2 (ORCPT ); Fri, 23 Oct 2020 10:10:28 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 46258113E; Fri, 23 Oct 2020 07:10:27 -0700 (PDT) Received: from [10.57.50.191] (unknown [10.57.50.191]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EDCFE3F66B; Fri, 23 Oct 2020 07:10:23 -0700 (PDT) Subject: Re: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek To: Yong Wu , Joerg Roedel , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Will Deacon Cc: Evan Green , Tomasz Figa , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, chao.hao@mediatek.com, ming-fan.chen@mediatek.com, Greg Kroah-Hartman , kernel-team@android.com References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-12-yong.wu@mediatek.com> From: Robin Murphy Message-ID: Date: Fri, 23 Oct 2020 15:10:22 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.3.3 MIME-Version: 1.0 In-Reply-To: <20200930070647.10188-12-yong.wu@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 2020-09-30 08:06, Yong Wu wrote: > The standard input iova bits is 32. MediaTek quad the lvl1 pagetable > (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach > 34bit. > > Signed-off-by: Yong Wu > --- > drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++--- > drivers/iommu/mtk_iommu.c | 2 +- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c > index 8362fdf76657..306bae2755ed 100644 > --- a/drivers/iommu/io-pgtable-arm-v7s.c > +++ b/drivers/iommu/io-pgtable-arm-v7s.c > @@ -50,10 +50,17 @@ > */ > #define ARM_V7S_ADDR_BITS 32 > #define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4) > +/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */ > +#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6) This should defined in terms of both lvl and cfg->ias. The formula here is nothing more than a disgusting trick I made up since a linear interpolation happened to fit the required numbers. That said, all of these bits pretending that short-descriptor is a well-defined recursive format only served to allow the rest of the code to look more like the LPAE code - IIRC they've already diverged a fair bit since then, so frankly a lot of this could stand to be unpicked and made considerably clearer by simply accepting that level 1 and level 2 are different from each other. Robin. > #define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl))) > #define ARM_V7S_TABLE_SHIFT 10 > > -#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl)) > +#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \ > + int _lvl = lvl; \ > + !arm_v7s_is_mtk_enabled(cfg) ? \ > + (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\ > +}) > + > #define ARM_V7S_TABLE_SIZE(lvl, cfg) \ > (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte)) > > @@ -63,7 +70,7 @@ > #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1) > #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \ > int _l = lvl; \ > - ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ > + ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \ > }) > > /* > @@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > { > struct arm_v7s_io_pgtable *data; > > - if (cfg->ias > ARM_V7S_ADDR_BITS) > + if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > return NULL; > > if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS)) > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index f6a2e3eb59d2..6e85c9976a33 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) > IO_PGTABLE_QUIRK_TLBI_ON_MAP | > IO_PGTABLE_QUIRK_ARM_MTK_EXT, > .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, > - .ias = 32, > + .ias = 34, > .oas = 35, > .tlb = &mtk_iommu_flush_ops, > .iommu_dev = data->dev, >