From: Jyri Sarha <jsarha@ti.com>
To: Yuti Amonkar <yamonkar@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<kishon@ti.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>,
<maxime@cerno.tech>
Cc: <tomi.valkeinen@ti.com>, <praneeth@ti.com>, <mparab@cadence.com>,
<sjakhade@cadence.com>
Subject: Re: [PATCH v2 01/14] dt-bindings: phy: Convert Cadence MHDP PHY bindings to YAML.
Date: Tue, 31 Dec 2019 14:24:07 +0200 [thread overview]
Message-ID: <a96aef7e-7c6d-5152-2e14-bb803d206cba@ti.com> (raw)
In-Reply-To: <1577114139-14984-2-git-send-email-yamonkar@cadence.com>
On 23/12/2019 17:15, Yuti Amonkar wrote:
> - Convert the MHDP PHY devicetree bindings to yaml schemas.
> - Rename DP PHY to have generic Torrent PHY nomrnclature.
> - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
> This will not affect ABI as the driver has never been functional,
> and therefore do not exist in any active use case
>
> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
> ---
> .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ----------
> .../bindings/phy/phy-cadence-torrent.yaml | 64 ++++++++++++++++++++++
> 2 files changed, 64 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> deleted file mode 100644
> index 7f49fd54e..0000000
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -Cadence MHDP DisplayPort SD0801 PHY binding
> -===========================================
> -
> -This binding describes the Cadence SD0801 PHY hardware included with
> -the Cadence MHDP DisplayPort controller.
> -
> --------------------------------------------------------------------------------
> -Required properties (controller (parent) node):
> -- compatible : Should be "cdns,dp-phy"
> -- reg : Defines the following sets of registers in the parent
> - mhdp device:
> - - Offset of the DPTX PHY configuration registers
> - - Offset of the SD0801 PHY configuration registers
> -- #phy-cells : from the generic PHY bindings, must be 0.
> -
> -Optional properties:
> -- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
> -- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
> - 2430, 2700, 3240, 4320, 5400 or 8100)
> --------------------------------------------------------------------------------
> -
> -Example:
> - dp_phy: phy@f0fb030a00 {
> - compatible = "cdns,dp-phy";
> - reg = <0xf0 0xfb030a00 0x0 0x00000040>,
> - <0xf0 0xfb500000 0x0 0x00100000>;
> - num_lanes = <4>;
> - max_bit_rate = <8100>;
> - #phy-cells = <0>;
> - };
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> new file mode 100644
> index 0000000..3587312
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -0,0 +1,64 @@
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence Torrent SD0801 PHY binding for DisplayPort
> +
> +description:
> + This binding describes the Cadence SD0801 PHY hardware included with
> + the Cadence MHDP DisplayPort controller.
> +
> +maintainers:
> + - Swapnil Jakhade <sjakhade@cadence.com>
> + - Yuti Amonkar <yamonkar@cadence.com>
> +
> +properties:
> + compatible:
> + const: cdns,torrent-phy
> +
> + reg:
> + items:
> + - description: Offset of the DPTX PHY configuration registers.
Isn't it possible to use torrent-phy in a configuration that does not
have dptx? Shouldn't the "dptx_phy" reg entry be optional?
BTW, I have no idea how to indicate in a yaml binding that some named
reg-entry is mandatory, and another is optional... anybody? Or is it
just something to explain in the description?
> + - description: Offset of the SD0801 PHY configuration registers.
> +
> + reg-names:
> + items:
> + - const: dptx_phy
> + - const: sd0801_phy
> +
> + "#phy-cells":
> + const: 0
> +
> + num_lanes:
> + description:
> + Number of DisplayPort lanes.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 4]
> +
> + max_bit_rate:
> + description:
> + Maximum DisplayPort link bit rate to use, in Mbps
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
> +
> +required:
> + - compatible
> + - reg
Shouldn't the reg-names be mandatory too?
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + dp_phy: phy@f0fb030a00 {
> + compatible = "cdns,torrent-phy";
> + reg = <0xf0 0xfb030a00 0x0 0x00000040>,
> + <0xf0 0xfb500000 0x0 0x00100000>;
There are no reg-names here?
> + num_lanes = <4>;
> + max_bit_rate = <8100>;
> + #phy-cells = <0>;
> + };
> +...
>
--
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next prev parent reply other threads:[~2019-12-31 12:24 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-23 15:15 [PATCH v2 00/14] PHY: Update Cadence Torrent PHY driver with reconfiguration Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 01/14] dt-bindings: phy: Convert Cadence MHDP PHY bindings to YAML Yuti Amonkar
2019-12-31 12:24 ` Jyri Sarha [this message]
2020-01-04 21:24 ` Rob Herring
2020-01-06 5:32 ` Kishon Vijay Abraham I
2019-12-23 15:15 ` [PATCH v2 02/14] phy: cadence-dp: Rename to phy-cadence-torrent Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 03/14] phy: cadence-torrent: Adopt Torrent nomenclature Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 04/14] phy: cadence-torrent: Add wrapper for PHY register access Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 05/14] phy: cadence-torrent: Add wrapper for DPTX " Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 06/14] phy: cadence-torrent: Refactor code for reusability Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 07/14] dt-bindings: phy: phy-cadence-torrent: Add clock bindings Yuti Amonkar
2019-12-31 12:28 ` Jyri Sarha
2020-01-04 21:25 ` Rob Herring
2019-12-23 15:15 ` [PATCH v2 08/14] phy: cadence-torrent: Add 19.2 MHz reference clock support Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 09/14] phy: cadence-torrent: Add PHY lane reset support Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 10/14] phy: cadence-torrent: Implement PHY configure APIs Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 11/14] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 12/14] phy: cadence-torrent: Use regmap to read and write DPTX " Yuti Amonkar
2019-12-23 15:15 ` [PATCH v2 13/14] dt-bindings: phy: phy-cadence-torrent: Add platform dependent compatible string Yuti Amonkar
2020-01-04 21:25 ` Rob Herring
2019-12-23 15:15 ` [PATCH v2 14/14] phy: cadence-torrent: Add platform dependent initialization structure Yuti Amonkar
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