From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vladimir Murzin Subject: Re: [PATCH 1/3] ARM: dts: stm32: add DMA memory pool on MCU which embed a cortex-M7 Date: Wed, 13 Dec 2017 10:06:36 +0000 Message-ID: References: <1513101746-18030-1-git-send-email-alexandre.torgue@st.com> <1513101746-18030-2-git-send-email-alexandre.torgue@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1513101746-18030-2-git-send-email-alexandre.torgue-qxv4g6HH51o@public.gmane.org> Content-Language: en-GB Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Alexandre Torgue , Maxime Coquelin , arnd-r2nGTMty4D4@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, patrice.chotard-qxv4g6HH51o@public.gmane.org, lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On 12/12/17 18:02, Alexandre Torgue wrote: > On cortex-M7 MCU, DMA have to use a non cache-able memory area. For this > reason a dedicated memory pool is created for DMA. > This patch creates a DMA memory pool of 1MB of each STM32 MCU which > embeds a cortex-M7 expect stm32f746-disco. Indeed, as stm32f746-disco has ^^^^^^ except? > only a 8MB SDRAM and it's tricky to reduce memory used by Kernel. I guess that 1MB is a kind of "should be enough" estimate, probably something along with [1] would give you exact numbers... > > Signed-off-by: Alexandre Torgue > > diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts > index 2d4e717..3f52a7b 100644 > --- a/arch/arm/boot/dts/stm32746g-eval.dts > +++ b/arch/arm/boot/dts/stm32746g-eval.dts > @@ -57,6 +57,19 @@ > reg = <0xc0000000 0x2000000>; > }; > > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + linux,dma { > + compatible = "shared-dma-pool"; > + linux,dma-default; > + no-map; > + reg = <0xc1f00000 0x100000>; > + }; > + }; > + > aliases { > serial0 = &usart1; > }; > diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts > index 4463ca1..08699a2 100644 > --- a/arch/arm/boot/dts/stm32f769-disco.dts > +++ b/arch/arm/boot/dts/stm32f769-disco.dts > @@ -57,6 +57,19 @@ > reg = <0xC0000000 0x1000000>; > }; > > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + linux,dma { > + compatible = "shared-dma-pool"; > + linux,dma-default; > + no-map; > + reg = <0xc0f00000 0x100000>; > + }; > + }; > + > aliases { > serial0 = &usart1; > }; > diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts > index 79e841d..104545a 100644 > --- a/arch/arm/boot/dts/stm32h743i-disco.dts > +++ b/arch/arm/boot/dts/stm32h743i-disco.dts > @@ -57,6 +57,19 @@ > reg = <0xd0000000 0x2000000>; > }; > > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + linux,dma { > + compatible = "shared-dma-pool"; > + linux,dma-default; > + no-map; > + reg = <0xc1f00000 0x100000>; > + }; > + }; > + > aliases { > serial0 = &usart2; > }; > diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts > index 9f0e72c..5bd4b16 100644 > --- a/arch/arm/boot/dts/stm32h743i-eval.dts > +++ b/arch/arm/boot/dts/stm32h743i-eval.dts > @@ -57,6 +57,19 @@ > reg = <0xd0000000 0x2000000>; > }; > > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + linux,dma { > + compatible = "shared-dma-pool"; > + linux,dma-default; > + no-map; > + reg = <0xc1f00000 0x100000>; > + }; > + }; > + > aliases { > serial0 = &usart1; > }; > Usage of dma-default looks correct to me, so FWIW Reviewed-by: Vladimir Murzin [1] https://lkml.org/lkml/2017/7/7/296 Vladimir -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html