From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sowjanya Komatineni Subject: Re: [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Date: Thu, 1 Aug 2019 11:06:07 -0700 Message-ID: References: <1564532424-10449-1-git-send-email-skomatineni@nvidia.com> <1564532424-10449-7-git-send-email-skomatineni@nvidia.com> <16cca6aa-1034-f38a-49d1-d87b37fb6bbb@gmail.com> <3b55a112-42a6-212b-beea-10b64d5341d9@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <3b55a112-42a6-212b-beea-10b64d5341d9@gmail.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Dmitry Osipenko , thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org On 8/1/19 3:53 AM, Dmitry Osipenko wrote: > 01.08.2019 0:04, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> On 7/31/19 4:11 AM, Dmitry Osipenko wrote: >>> 31.07.2019 3:20, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >>>> This patch adds support for saving OSC clock frequency and the >>>> drive-strength during OSC clock init and creates an API to restore >>>> OSC control register value from the saved context. >>>> >>>> This API is invoked by Tegra210 clock driver during system resume >>>> to restore the=C2=A0 OSC clock settings. >>>> >>>> Acked-by: Thierry Reding >>>> Signed-off-by: Sowjanya Komatineni >>>> --- >>>> =C2=A0 drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++ >>>> =C2=A0 drivers/clk/tegra/clk.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 1 + >>>> =C2=A0 2 files changed, 16 insertions(+) >>>> >>>> diff --git a/drivers/clk/tegra/clk-tegra-fixed.c >>>> b/drivers/clk/tegra/clk-tegra-fixed.c >>>> index 8d91b2b191cf..7c6c8abfcde6 100644 >>>> --- a/drivers/clk/tegra/clk-tegra-fixed.c >>>> +++ b/drivers/clk/tegra/clk-tegra-fixed.c >>>> @@ -17,6 +17,10 @@ >>>> =C2=A0 #define OSC_CTRL=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 0x50 >>>> =C2=A0 #define OSC_CTRL_OSC_FREQ_SHIFT=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 28 >>>> =C2=A0 #define OSC_CTRL_PLL_REF_DIV_SHIFT=C2=A0=C2=A0=C2=A0 26 >>>> +#define OSC_CTRL_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (0x3f2 |=C2=A0=C2=A0=C2=A0 \ >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (0xf << OSC_CTRL_OSC_FREQ_SHI= FT)) >>>> + >>>> +static u32 osc_ctrl_ctx; >>>> =C2=A0 =C2=A0 int __init tegra_osc_clk_init(void __iomem *clk_base, s= truct >>>> tegra_clk *clks, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned long *input_freqs, u= nsigned int num, >>>> @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem >>>> *clk_base, struct tegra_clk *clks, >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned osc_idx; >>>> =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 val =3D readl_relaxed(clk_base = + OSC_CTRL); >>>> +=C2=A0=C2=A0=C2=A0 osc_ctrl_ctx =3D val & OSC_CTRL_MASK; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 osc_idx =3D val >> OSC_CTRL_OSC_FREQ_S= HIFT; >>>> =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (osc_idx < num) >>>> @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk >>>> *tegra_clks) >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *dt_clk =3D cl= k; >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>> =C2=A0 } >>>> + >>>> +void tegra_clk_osc_resume(void __iomem *clk_base) >>>> +{ >>>> +=C2=A0=C2=A0=C2=A0 u32 val; >>>> + >>>> +=C2=A0=C2=A0=C2=A0 val =3D readl_relaxed(clk_base + OSC_CTRL) & ~OSC_= CTRL_MASK; >>>> +=C2=A0=C2=A0=C2=A0 val |=3D osc_ctrl_ctx; >>>> +=C2=A0=C2=A0=C2=A0 writel_relaxed(val, clk_base + OSC_CTRL); >>> Why a full raw u32 OSC_CTRL value couldn't be simply saved and restored= ? >> Storing and restoring only required fields to avoid accidental >> misconfiguration. >> >> OSC_CTRL register has other bits (PLL_REF_DIV) which are configured by >> BR depending on OSC_FREQ and also setting PLL_REF_DIV while PLLS are in >> use is not safe. > I'm looking at the clk-driver sources and see that none of the Tegra > drivers ever change the OSC_CTRL configuration, T30/114 even have > #defines for the OSC_CTRL that are unused. > > So, this leads to a question.. does any bootloader really ever change > the OSC_CTRL such that it differs after resume from suspend in > comparison to the value at the time of kernel's booting up? For Tegra210, bootloader programs OSC_CTRL register for drivestrength=20 programming. These settings need to be restored to the same on SC7 exit as they gets=20 reset during SC7 entry.