From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A693C43603 for ; Fri, 6 Dec 2019 07:28:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D1ED424679 for ; Fri, 6 Dec 2019 07:27:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726225AbfLFH17 (ORCPT ); Fri, 6 Dec 2019 02:27:59 -0500 Received: from mga07.intel.com ([134.134.136.100]:34291 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725858AbfLFH17 (ORCPT ); Fri, 6 Dec 2019 02:27:59 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2019 23:27:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,283,1571727600"; d="scan'208";a="411933028" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by fmsmga005.fm.intel.com with ESMTP; 05 Dec 2019 23:27:55 -0800 From: Dilip Kota To: lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@intel.com Cc: gustavo.pimentel@synopsys.com, andrew.murray@arm.com, robh@kernel.org, linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, Dilip Kota Subject: [PATCH v10 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Date: Fri, 6 Dec 2019 15:27:47 +0800 Message-Id: X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Intel PCIe is Synopsys based controller. Intel PCIe driver uses DesignWare PCIe framework for host initialization and register configurations. Changes on v10: Rebase the patches on mainline v5.4 Squashed the patch that fixes the below issue to this patch series. WARNING: unmet direct dependencies detected for PCIE_DW_HOST Depends on [n]: PCI [=y] && PCI_MSI_IRQ_DOMAIN [=n] Selected by [y]: - PCIE_INTEL_GW [=y] && PCI [=y] && OF [=y] && (X86 [=y] || COMPILE_TEST [=n]) "reportedby Randy Dunlap " Dilip Kota (3): dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller PCI: dwc: intel: PCIe RC controller driver PCI: artpec6: Configure FTS with dwc helper function .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++ drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec6.c | 8 +- drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 545 +++++++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 8 files changed, 766 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c -- 2.11.0