From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24386C433E0 for ; Thu, 25 Mar 2021 08:04:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D003F61A1F for ; Thu, 25 Mar 2021 08:04:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229659AbhCYIDt (ORCPT ); Thu, 25 Mar 2021 04:03:49 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:52505 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbhCYIDR (ORCPT ); Thu, 25 Mar 2021 04:03:17 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1616659397; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=oiHaIhlTw6rdY/eG8o6o068eoRZ8/VbUZDj7L5CPEUU=; b=VcZ/0MThy+3CzlC0acS9zv1wc8J/y8BYIFjPrWok/WGVbZ7pF2nMzpYHYUv5aOKI4hsk6dbZ JRqT+fD8ibetQuasVYOFFRgwR0JvMe8y5v5q7z+Kgs/mJAiAMHli9S+g2RQlW0vgTL8f01kU LEiWOU/DCwU2i0UaHzHCwEcjMuw= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 605c43b39a60a4db7cda2f22 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 25 Mar 2021 08:02:59 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 37E09C433CA; Thu, 25 Mar 2021 08:02:58 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2E06AC433ED; Thu, 25 Mar 2021 08:02:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2E06AC433ED Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sai Prakash Ranjan , Sibi Sankar , Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V2 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150 Date: Thu, 25 Mar 2021 13:32:31 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs interface to configure the register addresses.The options that the DCC hardware provides include reading from registers,writing to registers,first reading and then writing to registers and looping through the values of the same register. In certain cases a register write needs to be executed for accessing the rest of the registers, also the user might want to record the changing values of a register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by sysfs files once the driver is probed.The details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc. As an example let us consider a couple of debug scenarios where DCC has been proved to be effective for debugging purposes:- i)TimeStamp Related Issue On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper timestamp values. Proper timestamp: Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e Zero timestamp: Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 Now this is a non-fatal issue and doesn't need a system reset, but still needs to be rootcaused and fixed for those who do care about coresight etm traces. Since this is a timestamp issue, we would be looking for any timestamp related clocks and such. o we get all the clk register details from IP documentation and configure it via DCC config syfs node. Before that we set the current linked list. /* Set the current linked list */ echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list /* Program the linked list with the addresses */ echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config ..... and so on for other timestamp related clk registers /* Other way of specifying is in "addr len" pair, in below case it specifies to capture 4 words starting 0x10C004 */ echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config /* Enable DCC */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable /* Run the timestamp test for working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram1.bin /* Run the timestamp test for non-working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram2.bin Get the parser from [1] and checkout the latest branch. /* Parse the SRAM bin */ python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python dcc_parser.py -s dcc_sram2.bin --v2 -o output/ Sample parsed output of dcc_sram1.bin: 03/14/21 Linux DCC Parser next_ll_offset : 0x1c ii)NOC register errors A particular class of registers called NOC which are functional registers was reporting errors while logging the values.To trace these errors the DCC has been used effectively. The steps followed were similar to the ones mentioned above. In addition to NOC registers a few other dependent registers were configured in DCC to monitor it's values during a crash. A look at the dependent register values revealed that the crash was happening due to a secured access to one of these dependent registers. All these debugging activity and finding the root cause was achieved using DCC. DCC parser is available at the following open source location https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser Souradeep Chowdhury (5): dt-bindings: Added the yaml bindings for DCC soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC) DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver support arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node Documentation/ABI/testing/sysfs-driver-dcc | 114 ++ .../devicetree/bindings/arm/msm/qcom,dcc.yaml | 49 + MAINTAINERS | 8 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 + drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1549 ++++++++++++++++++++ 7 files changed, 1736 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml create mode 100644 drivers/soc/qcom/dcc.c -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 871C0C433E0 for ; Mon, 29 Mar 2021 06:33:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5A0D961966 for ; Mon, 29 Mar 2021 06:33:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230226AbhC2GdK (ORCPT ); Mon, 29 Mar 2021 02:33:10 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:25892 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230052AbhC2GdF (ORCPT ); Mon, 29 Mar 2021 02:33:05 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1616999585; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=oiHaIhlTw6rdY/eG8o6o068eoRZ8/VbUZDj7L5CPEUU=; b=wesJG5D7qSV5jWD2gd9q5Vn1KNaR/8YohH9MhnCrTDnPCP6AfRwslxOWNKp/XOj/02WZQFno xgdjKPtrUzVzWnlcSZrAbhfsfYMkdXMu7p1A1bK8vcdLoxHAbHECOFo9ZCnza4ljSbHHaIXn TTfFSOuHX6CmC2f6KvkN2pppGIo= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-west-2.postgun.com with SMTP id 6061748d3f0cbfdaf2090d98 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 29 Mar 2021 06:32:45 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AB945C433C6; Mon, 29 Mar 2021 06:32:42 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 51B6BC433CA; Mon, 29 Mar 2021 06:32:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 51B6BC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sai Prakash Ranjan , Sibi Sankar , Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V3 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150 Date: Mon, 29 Mar 2021 12:02:21 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Message-ID: <20210329063221.GeCnVaNBLmqbMtUdPM0JlmOmLp3Wiglo52P_yGLCkto@z> DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs interface to configure the register addresses.The options that the DCC hardware provides include reading from registers,writing to registers,first reading and then writing to registers and looping through the values of the same register. In certain cases a register write needs to be executed for accessing the rest of the registers, also the user might want to record the changing values of a register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by sysfs files once the driver is probed.The details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc. As an example let us consider a couple of debug scenarios where DCC has been proved to be effective for debugging purposes:- i)TimeStamp Related Issue On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper timestamp values. Proper timestamp: Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e Zero timestamp: Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 Now this is a non-fatal issue and doesn't need a system reset, but still needs to be rootcaused and fixed for those who do care about coresight etm traces. Since this is a timestamp issue, we would be looking for any timestamp related clocks and such. o we get all the clk register details from IP documentation and configure it via DCC config syfs node. Before that we set the current linked list. /* Set the current linked list */ echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list /* Program the linked list with the addresses */ echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config ..... and so on for other timestamp related clk registers /* Other way of specifying is in "addr len" pair, in below case it specifies to capture 4 words starting 0x10C004 */ echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config /* Enable DCC */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable /* Run the timestamp test for working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram1.bin /* Run the timestamp test for non-working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram2.bin Get the parser from [1] and checkout the latest branch. /* Parse the SRAM bin */ python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python dcc_parser.py -s dcc_sram2.bin --v2 -o output/ Sample parsed output of dcc_sram1.bin: 03/14/21 Linux DCC Parser next_ll_offset : 0x1c ii)NOC register errors A particular class of registers called NOC which are functional registers was reporting errors while logging the values.To trace these errors the DCC has been used effectively. The steps followed were similar to the ones mentioned above. In addition to NOC registers a few other dependent registers were configured in DCC to monitor it's values during a crash. A look at the dependent register values revealed that the crash was happening due to a secured access to one of these dependent registers. All these debugging activity and finding the root cause was achieved using DCC. DCC parser is available at the following open source location https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser Souradeep Chowdhury (5): dt-bindings: Added the yaml bindings for DCC soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC) DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver support arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node Documentation/ABI/testing/sysfs-driver-dcc | 114 ++ .../devicetree/bindings/arm/msm/qcom,dcc.yaml | 49 + MAINTAINERS | 8 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 + drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1549 ++++++++++++++++++++ 7 files changed, 1736 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml create mode 100644 drivers/soc/qcom/dcc.c -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E16FCC433E0 for ; Mon, 29 Mar 2021 07:50:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9DF6D61936 for ; Mon, 29 Mar 2021 07:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbhC2Hu0 (ORCPT ); Mon, 29 Mar 2021 03:50:26 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:26303 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231154AbhC2HuI (ORCPT ); Mon, 29 Mar 2021 03:50:08 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1617004208; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=cpkO7rqDsm2ojWg0iRVpxJyqomqOJeB3iE7+en0L+/w=; b=Lkmh1C9frsOo+sRj+ubDAjLFfRDWzrYwVMTc9jXOglImA/9P4gCtaxaAOPod95pbxX3l+QB+ PnbEc4JuSLmaYMMLxklqdUAucqCNdsAIQe0vJocbCrIoLjpw3tyTbi4+qyF77z1m5I/D3WCI q0fxIJyCvKoTgCYecIZfupcjxPg= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-east-1.postgun.com with SMTP id 606186af0a4a07ffda82cac0 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 29 Mar 2021 07:50:07 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C8AE1C43462; Mon, 29 Mar 2021 07:50:06 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6CA9EC433C6; Mon, 29 Mar 2021 07:50:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6CA9EC433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Andy Gross , Bjorn Andersson , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sai Prakash Ranjan , Sibi Sankar , Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [Resend PATCH V3 0/5] Add driver support for Data Capture and Compare Engine(DCC) for SM8150 Date: Mon, 29 Mar 2021 13:19:09 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Message-ID: <20210329074909.vpO1kbU39ZSxJpJFZqQc-9i_h5ucqyd4gqZK3a1DQtg@z> DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs interface to configure the register addresses.The options that the DCC hardware provides include reading from registers,writing to registers,first reading and then writing to registers and looping through the values of the same register. In certain cases a register write needs to be executed for accessing the rest of the registers, also the user might want to record the changing values of a register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by sysfs files once the driver is probed.The details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc. As an example let us consider a couple of debug scenarios where DCC has been proved to be effective for debugging purposes:- i)TimeStamp Related Issue On SC7180, there was a coresight timestamp issue where it would occasionally be all 0 instead of proper timestamp values. Proper timestamp: Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e Zero timestamp: Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2 Now this is a non-fatal issue and doesn't need a system reset, but still needs to be rootcaused and fixed for those who do care about coresight etm traces. Since this is a timestamp issue, we would be looking for any timestamp related clocks and such. o we get all the clk register details from IP documentation and configure it via DCC config syfs node. Before that we set the current linked list. /* Set the current linked list */ echo 3 > /sys/bus/platform/devices/10a2000.dcc/curr_list /* Program the linked list with the addresses */ echo 0x10c004 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c008 > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c00c > /sys/bus/platform/devices/10a2000.dcc/config echo 0x10c010 > /sys/bus/platform/devices/10a2000.dcc/config ..... and so on for other timestamp related clk registers /* Other way of specifying is in "addr len" pair, in below case it specifies to capture 4 words starting 0x10C004 */ echo 0x10C004 4 > /sys/bus/platform/devices/10a2000.dcc/config /* Enable DCC */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/enable /* Run the timestamp test for working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram1.bin /* Run the timestamp test for non-working case */ /* Send SW trigger */ echo 1 > /sys/bus/platform/devices/10a2000.dcc/trigger /* Read SRAM */ cat /dev/dcc_sram > dcc_sram2.bin Get the parser from [1] and checkout the latest branch. /* Parse the SRAM bin */ python dcc_parser.py -s dcc_sram1.bin --v2 -o output/ python dcc_parser.py -s dcc_sram2.bin --v2 -o output/ Sample parsed output of dcc_sram1.bin: 03/14/21 Linux DCC Parser next_ll_offset : 0x1c ii)NOC register errors A particular class of registers called NOC which are functional registers was reporting errors while logging the values.To trace these errors the DCC has been used effectively. The steps followed were similar to the ones mentioned above. In addition to NOC registers a few other dependent registers were configured in DCC to monitor it's values during a crash. A look at the dependent register values revealed that the crash was happening due to a secured access to one of these dependent registers. All these debugging activity and finding the root cause was achieved using DCC. DCC parser is available at the following open source location https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser Changes in v3: * Collect the review tag * Fix the dtsi issue reported in v2 Souradeep Chowdhury (5): dt-bindings: Added the yaml bindings for DCC soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC) DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver MAINTAINERS:Add the entry for DCC(Data Capture and Compare) driver support arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node Documentation/ABI/testing/sysfs-driver-dcc | 114 ++ .../devicetree/bindings/arm/msm/qcom,dcc.yaml | 49 + MAINTAINERS | 8 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 + drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1549 ++++++++++++++++++++ 7 files changed, 1736 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml create mode 100644 drivers/soc/qcom/dcc.c -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation