[PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[Shawn Lin]

This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.

Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..ba8c406
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,22 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+
+Example:
+
+grf: syscon@ff770000 {
+	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	...
+
+	pcie_phy: phy@e220 {
+		compatible = "rockchip,rk3399-pcie-phy";
+		#phy-cells = <0>;
+	};
+};
+
-- 
2.3.7


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Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[Rob Herring]

gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
> 
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> 
>  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0
> +
> +Example:
> +
> +grf: syscon@ff770000 {
> +	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	...
> +
> +	pcie_phy: phy@e220 {

unit-address needs a reg property or drop the unit address. I'd do the 
former if there's a register range you can describe here.


> +		compatible = "rockchip,rk3399-pcie-phy";
> +		#phy-cells = <0>;
> +	};
> +};
> +
> -- 
> 2.3.7
> 
> 
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Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[Heiko Stübner]

Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring:
> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
> > This patch adds a binding that describes the Rockchip PCIe PHY
> > found on Rockchip SoCs PCIe interface.
> > 
> > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> > ---
> > 
> >  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22
> >  ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt> 
> > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
> > mode 100644
> > index 0000000..ba8c406
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> > @@ -0,0 +1,22 @@
> > +Rockchip PCIE PHY
> > +-----------------------
> > +
> > +Required properties:
> > + - compatible: rockchip,rk3399-pcie-phy
> > + - #phy-cells: must be 0
> > +
> > +Example:
> > +
> > +grf: syscon@ff770000 {
> > +	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	...
> > +
> > +	pcie_phy: phy@e220 {
> 
> unit-address needs a reg property or drop the unit address. I'd do the
> former if there's a register range you can describe here.

Hmm, I think I'd suggest going the other way - call the node pcie-phy .

While the General Register Files do contain some specific address ranges (like 
for the emmc phy, or some performance monitor things), the register at 0xe220 
is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting 
bits.

Specifying register ranges suggests some form of exclusivity to me - which is 
just great for things like the emmc phy that has an actual range, but for a 
device being controlled from some shared register.


Heiko

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Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[Doug Anderson]

Shawn,

On Wed, Jun 8, 2016 at 12:25 AM, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> This patch adds a binding that describes the Rockchip PCIe PHY
> found on Rockchip SoCs PCIe interface.
>
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>
>  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> new file mode 100644
> index 0000000..ba8c406
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip PCIE PHY
> +-----------------------
> +
> +Required properties:
> + - compatible: rockchip,rk3399-pcie-phy
> + - #phy-cells: must be 0

Code also requires reset and clock.

clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
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Re: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY

[Shawn Lin]

On 2016/6/9 4:40, Heiko Stübner wrote:
> Am Mittwoch, 8. Juni 2016, 15:29:00 schrieb Rob Herring:
>> gOn Wed, Jun 08, 2016 at 03:25:08PM +0800, Shawn Lin wrote:
>>> This patch adds a binding that describes the Rockchip PCIe PHY
>>> found on Rockchip SoCs PCIe interface.
>>>
>>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>> ---
>>>
>>>  .../devicetree/bindings/phy/rockchip-pcie-phy.txt  | 22
>>>  ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
>>>  create mode 100644
>>>  Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt>
>>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>>> b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file
>>> mode 100644
>>> index 0000000..ba8c406
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
>>> @@ -0,0 +1,22 @@
>>> +Rockchip PCIE PHY
>>> +-----------------------
>>> +
>>> +Required properties:
>>> + - compatible: rockchip,rk3399-pcie-phy
>>> + - #phy-cells: must be 0
>>> +
>>> +Example:
>>> +
>>> +grf: syscon@ff770000 {
>>> +	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
>>> +	#address-cells = <1>;
>>> +	#size-cells = <1>;
>>> +
>>> +	...
>>> +
>>> +	pcie_phy: phy@e220 {
>>
>> unit-address needs a reg property or drop the unit address. I'd do the
>> former if there's a register range you can describe here.
>
> Hmm, I think I'd suggest going the other way - call the node pcie-phy .

pcie phy does not cantain a reg range, so I will drop the unit-address.

>
> While the General Register Files do contain some specific address ranges (like
> for the emmc phy, or some performance monitor things), the register at 0xe220
> is a shared register (GRF_SOC_CON8), containing both i2s and pcie setting
> bits.

yes, we only need two bits: test_addr(for pcie phy's internal configure
address) and test_i(corresponding value for the address given) whthin
GRF_SOC_CON8 to W/R the phy.

>
> Specifying register ranges suggests some form of exclusivity to me - which is
> just great for things like the emmc phy that has an actual range, but for a
> device being controlled from some shared register.
>
>
> Heiko
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>


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Best Regards
Shawn Lin