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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id t204sm318596lff.87.2021.11.08.13.22.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Nov 2021 13:22:57 -0800 (PST) Message-ID: Date: Mon, 8 Nov 2021 22:22:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio Content-Language: en-US To: conor.dooley@microchip.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, a.zummo@towertech.it, alexandre.belloni@bootlin.com, broonie@kernel.org, gregkh@linuxfoundation.org, lewis.hanly@microchip.com, daire.mcnamara@microchip.com, atish.patra@wdc.com, ivan.griffin@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-riscv@lists.infradead.org, linux-crypto@vger.kernel.org, linux-rtc@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Cc: geert@linux-m68k.org, bin.meng@windriver.com References: <20211108150554.4457-1-conor.dooley@microchip.com> <20211108150554.4457-10-conor.dooley@microchip.com> From: Krzysztof Kozlowski In-Reply-To: <20211108150554.4457-10-conor.dooley@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/11/2021 16:05, conor.dooley@microchip.com wrote: > From: Conor Dooley > > Add device tree bindings for the gpio controller on > the Microchip PolarFire SoC. > > Signed-off-by: Conor Dooley > --- > .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++ > 1 file changed, 108 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml > new file mode 100644 > index 000000000000..067019ddc1f7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml > @@ -0,0 +1,108 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip MPFS GPIO Controller Device Tree Bindings > + > +maintainers: > + - Conor Dooley > + > +description: | > + This GPIO controller is found on the Microchip PolarFire SoC. If "Microchip MPFS" means "Microchip PolarFire SoC", then this is duplicating the title. Similarly to your previous patches. Skip it then, there is no point to have descriptions which are obvious or duplicating existing information. > + > +properties: > + compatible: > + items: > + - enum: > + - microchip,mpfs-gpio > + - microsemi,ms-pf-mss-gpio > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: > + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. > + minItems: 1 > + maxItems: 32 > + > + interrupt-controller: true > + > + clocks: > + maxItems: 1 > + > + "#gpio-cells": > + const: 2 > + > + ngpios: > + description: > + The number of GPIOs available. > + minimum: 1 > + maximum: 32 > + default: 32 > + > + gpio-controller: true > + > +required: > + - compatible > + - reg > + - interrupts > + - "#interrupt-cells" > + - "#gpio-cells" > + - gpio-controller > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include "dt-bindings/clock/microchip,mpfs-clock.h" > + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + gpio2: gpio@20122000 { > + compatible = "microchip,mpfs-gpio"; > + reg = <0x0 0x20122000 0x0 0x1000>; > + clocks = <&clkcfg CLK_GPIO2>; > + interrupt-parent = <&plic>; > + interrupts = + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT > + PLIC_INT_GPIO2_NON_DIRECT>; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; Skip status=disabled. > + }; > + }; > +... > Best regards, Krzysztof