From: Dilip Kota <eswara.kota@linux.intel.com>
To: lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
andrew.murray@arm.com, robh@kernel.org,
linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com,
cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH v11 3/3] PCI: artpec6: Configure FTS with dwc helper function
Date: Mon, 9 Dec 2019 11:20:06 +0800 [thread overview]
Message-ID: <d862101a58286c30636a5f4671861ac4f076bfb8.1575860791.git.eswara.kota@linux.intel.com> (raw)
In-Reply-To: <cover.1575860791.git.eswara.kota@linux.intel.com>
In-Reply-To: <cover.1575860791.git.eswara.kota@linux.intel.com>
Use DesignWare helper functions to configure Fast Training
Sequence. Drop the respective code in the driver.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index 9e2482bd7b6d..28d5a1095200 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
#define ACK_N_FTS_MASK GENMASK(15, 8)
#define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
-#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
-#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
-
/* ARTPEC-6 specific registers */
#define PCIECFG 0x18
#define PCIECFG_DBG_OEN BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
* Set the Number of Fast Training Sequences that the core
* advertises as its N_FTS during Gen2 or Gen3 link training.
*/
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
- val &= ~FAST_TRAINING_SEQ_MASK;
- val |= FAST_TRAINING_SEQ(180);
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_link_set_n_fts(pci, 180);
}
static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
--
2.11.0
next prev parent reply other threads:[~2019-12-09 3:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 3:20 [PATCH v11 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-12-09 3:20 ` [PATCH v11 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-12-19 16:32 ` Rob Herring
2019-12-20 9:26 ` Dilip Kota
2019-12-09 3:20 ` [PATCH v11 2/3] PCI: dwc: intel: PCIe RC controller driver Dilip Kota
2019-12-09 3:20 ` Dilip Kota [this message]
2019-12-09 13:21 ` [PATCH v11 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Andrew Murray
2019-12-09 14:17 ` Lorenzo Pieralisi
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