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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id h6-20020adffd46000000b0021b96cdf68fsm2770955wrs.97.2022.06.24.10.12.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jun 2022 10:12:41 -0700 (PDT) Message-ID: Date: Fri, 24 Jun 2022 19:12:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Content-Language: en-US To: Thierry Reding Cc: Bhadram Varka , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jonathanh@nvidia.com, kuba@kernel.org, catalin.marinas@arm.com, will@kernel.org, Thierry Reding References: <20220623074615.56418-1-vbhadram@nvidia.com> <20220623074615.56418-2-vbhadram@nvidia.com> <53e8aa2f-f5f6-43d9-c167-ec5c5818dfb0@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 24/06/2022 18:21, Thierry Reding wrote: > On Fri, Jun 24, 2022 at 06:02:58PM +0200, Krzysztof Kozlowski wrote: >> On 23/06/2022 09:46, Bhadram Varka wrote: >>> From: Thierry Reding >>> >>> Add the clocks and resets used by the MGBE Ethernet hardware found on >>> Tegra234 SoCs. >>> >>> Signed-off-by: Thierry Reding >>> Signed-off-by: Bhadram Varka >>> --- >>> include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++ >>> include/dt-bindings/reset/tegra234-reset.h | 8 ++ >>> 2 files changed, 109 insertions(+) >>> >>> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h >>> index bd4c3086a2da..bab85d9ba8cd 100644 >>> --- a/include/dt-bindings/clock/tegra234-clock.h >>> +++ b/include/dt-bindings/clock/tegra234-clock.h >>> @@ -164,10 +164,111 @@ >>> #define TEGRA234_CLK_PEX1_C5_CORE 225U >>> /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ >>> #define TEGRA234_CLK_PLLC4 237U >>> +/** @brief RX clock recovered from MGBE0 lane input */ >> >> The IDs should be abstract integer incremented by one, without any >> holes. I guess the issue was here before, so it's fine but I'll start >> complaining at some point :) > > These IDs originate from firmware and therefore are more like hardware > IDs rather than an arbitrary enumeration. These will be used directly in > IPC calls with the firmware to reference individual clocks and resets. If they are actually shared with firmware, it's fine. Thanks for explanation. > We've adopted these 1:1 in order to avoid adding an extra level of > indirection (via some lookup table) in the kernel. This if fine, but some folks (including myself once...) define in bindings register values and offsets without any actual need. I was afraid that's the case here. Best regards, Krzysztof