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From: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>,
	Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Brian Norris
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	Adrian Hunter
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	"open list:ARM/Rockchip SoC..."
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Subject: Re: [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399
Date: Tue, 14 Jun 2016 08:59:15 +0800	[thread overview]
Message-ID: <da1c9ae9-71d9-6e9d-7b9f-08485ee9178e@rock-chips.com> (raw)
In-Reply-To: <CAD=FV=UL5tU8RWtHF=-pE8SA0jUcBsqQDOU0BrruXOF7yGh5xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

在 2016/6/14 8:43, Doug Anderson 写道:
> Hi,
>
> On Mon, Jun 13, 2016 at 5:14 PM, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>>>> It's broken when reading capabilities reg on RK3399 platform
>>>> which means you should get it via clk framework. But you should consider
>>>> the non-broken case.
>>>
>>>
>>> I'm afraid I don't understand.  Can you elaborate?  Are you saying if
>>> things weren't broken then we wouldn't have to ask the common clock
>>> framework for this?  Where would we get this value?
>>
>>
>>
>> I mean bascially we should get baseclk from capabilities register[15:8]
>> (offset 0x40@sdhci), namely EMMCCORE_CAP on TRM. Only when you get 0x0
>> from there, can you consider to get it from clock framework.
>
> Ah, got it!
>
> I guess I would be super surprised if an SoC implemented
> register[15:8] but still then required you to manually copy that value
> to corecfg_baseclkfreq.  Presumably nobody would be crazy enough to
> try to measure the clock rate in the SDHCI driver, so this would
> probably only be non-zero where the SDHCI clock is totally fixed.
> ...in that case probably the SoC designer would also put a default
> value in corecfg_baseclkfreq that matched (and maybe even make
> corecfg_baseclkfreq read-only?).

yes, you could see some others similar capabilities case like
timeoutclkfreq or preset value, etc. SDHCI hope Soc designer to
implement them within the controller but not mandatory.

>
> Even in the case that an SoC designer didn't put a value into
> corecfg_baseclkfreq that matched register[15:8], it seems very likely
> that the rate returned from the clk_get_rate() would match.
>
> I guess what I'm saying is that, to me, it seems like my patch isn't
> broken in any real systems.  If we ever find a system that needs this
> behavior in the future, we can add it.  Until then, it seems like my
> patch would be fine.  Do you agree?

I agree. But from the code itself, we should still use
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN to see if we could get
it from internal register in case of some platforms don't
provide the clk stuff.. Sounds sane? :)

>
> Note: right now we only provide a register map for rk3399, so
> certainly we can't be breaking any other SoCs with our current method.
>
>
>> I don't see a reason to check the return code here.  Specifically:
>>>
>>> * If this is a SoC where you don't need to write corecfg_baseclkfreq
>>> then we need do nothing about this error.
>>>
>>> * If the regmap write failed (which would be terribly unexpected for a
>>> memory mapped register) then we've already printed an error (in
>>> sdhci_arasan_syscon_write).  Best course of action seems to keep going
>>> and try anyway.
>>>
>>>
>>> I don't think a retry is likely to help anything.
>>
>>
>> Well, I saw you add a return value for sdhci_arasan_syscon_write, so
>> should we remove it?
>
> It was presuming that there might be future callers who might want to
> write other corecfg registers and might need to know whether the write
> worked or not.  Since having the return value doesn't hurt anything
> I'd rather leave it in.  If you really want me to remove it, though, I
> will.  Just let me know.

Ahh, it's trivial, so keep it if you want.

>
>
> -Doug
>
>
>


-- 
Best Regards
Shawn Lin

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  parent reply	other threads:[~2016-06-14  0:59 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-07 22:44 [PATCH 0/11] Changes to support 150 MHz eMMC " Douglas Anderson
     [not found] ` <1465339484-969-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-07 22:44   ` [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
     [not found]     ` <1465339484-969-2-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  7:58       ` Shawn Lin
     [not found]         ` <3e19ff54-ee4a-c208-e137-1c0f8022f6b3-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:07           ` Doug Anderson
2016-06-07 22:44   ` [PATCH 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
     [not found]     ` <1465339484-969-3-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  8:08       ` Shawn Lin
2016-06-13 23:06         ` Doug Anderson
2016-06-07 22:44   ` [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-08 20:17     ` Rob Herring
2016-06-13  8:18     ` Shawn Lin
     [not found]       ` <45a7e8c7-5bd4-8c40-004a-b8906eff881a-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13  9:32         ` Heiko Stübner
2016-06-13 23:07       ` Doug Anderson
2016-06-07 22:44   ` [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-07 22:44   ` [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-10 13:36     ` Rob Herring
2016-06-13 23:05       ` Doug Anderson
2016-06-07 22:44   ` [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson
2016-06-13  8:56     ` Shawn Lin
2016-06-13 23:05       ` Doug Anderson
2016-06-07 22:44 ` [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-13  8:36   ` Shawn Lin
     [not found]     ` <f5dcc018-bd60-87a7-798b-efc261e443dd-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:06       ` Doug Anderson
2016-06-14  0:14         ` Shawn Lin
     [not found]           ` <47a2dcd9-9c3c-8fde-2be0-40e305c25e8d-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14  0:43             ` Doug Anderson
     [not found]               ` <CAD=FV=UL5tU8RWtHF=-pE8SA0jUcBsqQDOU0BrruXOF7yGh5xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-14  0:59                 ` Shawn Lin [this message]
2016-06-14  2:13                   ` Doug Anderson
2016-06-16  1:06                     ` Shawn Lin
2016-06-07 22:44 ` [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-07 22:44 ` [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-08 20:19   ` Rob Herring
2016-06-08 20:52     ` Doug Anderson
2016-06-10 13:10       ` Rob Herring
2016-06-13 23:05         ` Doug Anderson
2016-06-07 22:44 ` [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on " Douglas Anderson
     [not found]   ` <1465339484-969-10-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  8:54     ` Shawn Lin
2016-06-13 23:05       ` Doug Anderson
2016-06-14  0:24         ` Shawn Lin
     [not found]           ` <036b0349-8343-f5de-7215-5a0843ebc6a9-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14  0:45             ` Doug Anderson
2016-06-07 22:44 ` [PATCH 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson

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