* [PATCH 0/4] Update sdmmc nodes for STM32MP1
@ 2019-11-06 10:09 Yann Gautier
2019-11-06 10:09 ` [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 Yann Gautier
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Yann Gautier @ 2019-11-06 10:09 UTC (permalink / raw)
To: alexandre.torgue
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel, Yann Gautier
The STM32MP1 SoC embeds 3 instances of the SDMMC internal peripheral.
The sdmmc2 and sdmmc3 nodes are added in the SoC DT file, as well as
the required pins configuration.
The boards DT files are also updated:
- An eMMC is connected on SDMMC2 on STM32MP157C-ED1 and EV1 boards
- SDMMC3 can be used on the GPIO expansion pins on EV1 and DK1/DK2
boards.
Yann Gautier (4):
ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157
ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC
ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board
ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 200 +++++++++++++++++++++-
arch/arm/boot/dts/stm32mp157a-dk1.dts | 12 ++
arch/arm/boot/dts/stm32mp157c-ed1.dts | 16 ++
arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 ++
arch/arm/boot/dts/stm32mp157c.dtsi | 33 +++-
5 files changed, 263 insertions(+), 10 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
@ 2019-11-06 10:09 ` Yann Gautier
2019-11-06 10:09 ` [PATCH 2/4] ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC Yann Gautier
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yann Gautier @ 2019-11-06 10:09 UTC (permalink / raw)
To: alexandre.torgue
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel, Yann Gautier,
Ludovic Barre
Relax sdmmc1 pins slew-rate to minimize peak currents.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 28 +++++++++++++++--------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 0a3a7d66737b..2904bc8c6a41 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -731,14 +731,19 @@
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
+ pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
drive-push-pull;
bias-disable;
};
@@ -749,15 +754,20 @@
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
drive-push-pull;
bias-disable;
};
- pins2{
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-open-drain;
bias-disable;
};
@@ -779,7 +789,7 @@
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
+ slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
2019-11-06 10:09 ` [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 Yann Gautier
@ 2019-11-06 10:09 ` Yann Gautier
2019-11-06 10:09 ` [PATCH 3/4] ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board Yann Gautier
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yann Gautier @ 2019-11-06 10:09 UTC (permalink / raw)
To: alexandre.torgue
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel, Yann Gautier,
Ludovic Barre
The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral.
The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
arch/arm/boot/dts/stm32mp157c.dtsi | 33 +++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 9b11654a0a39..fa71aac0b0c5 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -1030,6 +1030,21 @@
};
};
+ sdmmc3: sdmmc@48004000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x48004000 0x400>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC3_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC3_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
usbotg_hs: usb-otg@49000000 {
compatible = "snps,dwc2";
reg = <0x49000000 0x10000>;
@@ -1295,13 +1310,29 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
+ interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: sdmmc@58007000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x58007000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
};
crc1: crc@58009000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
2019-11-06 10:09 ` [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 Yann Gautier
2019-11-06 10:09 ` [PATCH 2/4] ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC Yann Gautier
@ 2019-11-06 10:09 ` Yann Gautier
2019-11-06 10:09 ` [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Yann Gautier
2019-11-15 10:50 ` [PATCH 0/4] Update sdmmc nodes for STM32MP1 Alexandre Torgue
4 siblings, 0 replies; 6+ messages in thread
From: Yann Gautier @ 2019-11-06 10:09 UTC (permalink / raw)
To: alexandre.torgue
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel, Yann Gautier,
Ludovic Barre
On STM32MP157C-ED1, the eMMC is connected on instance 2 of SDMMC
peripheral. The sdmmc2 node is then added in the board DT file, as well as
the pins nodes in the pinctrl file.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 118 ++++++++++++++++++++++
arch/arm/boot/dts/stm32mp157c-ed1.dts | 16 +++
2 files changed, 134 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 2904bc8c6a41..a907d93f8916 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -808,6 +808,124 @@
};
};
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
spdifrx_pins_a: spdifrx-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 1d426ea8bdaf..b40a6b9a7aa6 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -302,6 +302,22 @@
status = "okay";
};
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
&timers6 {
status = "okay";
/* spare dmas for other usage */
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
` (2 preceding siblings ...)
2019-11-06 10:09 ` [PATCH 3/4] ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board Yann Gautier
@ 2019-11-06 10:09 ` Yann Gautier
2019-11-15 10:50 ` [PATCH 0/4] Update sdmmc nodes for STM32MP1 Alexandre Torgue
4 siblings, 0 replies; 6+ messages in thread
From: Yann Gautier @ 2019-11-06 10:09 UTC (permalink / raw)
To: alexandre.torgue
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel, Yann Gautier,
Ludovic Barre
On STM32MP1 EVAL and DISCOVERY boards, the SDMMC3 internal peripheral
can be used through the GPIO extension connector. The sdmmc3 node is then
added in the boards DT files, and the required pins are also added.
The node status is disabled as there is no device connected by default.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 54 +++++++++++++++++++++++
arch/arm/boot/dts/stm32mp157a-dk1.dts | 12 +++++
arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 +++++
3 files changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index a907d93f8916..d31a4661f7b5 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -926,6 +926,60 @@
};
};
+ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
+ };
+ };
+
spdifrx_pins_a: spdifrx-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 0615d1c8a6fc..b86c32e6a829 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -444,6 +444,18 @@
status = "okay";
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 89d29b50c3f4..d047901c51ea 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -293,6 +293,18 @@
};
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] Update sdmmc nodes for STM32MP1
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
` (3 preceding siblings ...)
2019-11-06 10:09 ` [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Yann Gautier
@ 2019-11-15 10:50 ` Alexandre Torgue
4 siblings, 0 replies; 6+ messages in thread
From: Alexandre Torgue @ 2019-11-15 10:50 UTC (permalink / raw)
To: Yann Gautier
Cc: mcoquelin.stm32, robh+dt, mark.rutland, linux-stm32,
linux-arm-kernel, devicetree, linux-kernel
Hi Yann
On 11/6/19 11:09 AM, Yann Gautier wrote:
> The STM32MP1 SoC embeds 3 instances of the SDMMC internal peripheral.
> The sdmmc2 and sdmmc3 nodes are added in the SoC DT file, as well as
> the required pins configuration.
> The boards DT files are also updated:
> - An eMMC is connected on SDMMC2 on STM32MP157C-ED1 and EV1 boards
> - SDMMC3 can be used on the GPIO expansion pins on EV1 and DK1/DK2
> boards.
>
> Yann Gautier (4):
> ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157
> ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC
> ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board
> ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards
>
> arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 200 +++++++++++++++++++++-
> arch/arm/boot/dts/stm32mp157a-dk1.dts | 12 ++
> arch/arm/boot/dts/stm32mp157c-ed1.dts | 16 ++
> arch/arm/boot/dts/stm32mp157c-ev1.dts | 12 ++
> arch/arm/boot/dts/stm32mp157c.dtsi | 33 +++-
> 5 files changed, 263 insertions(+), 10 deletions(-)
>
Series applied on stm32-next.
Regards
Alex
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-11-15 10:50 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-06 10:09 [PATCH 0/4] Update sdmmc nodes for STM32MP1 Yann Gautier
2019-11-06 10:09 ` [PATCH 1/4] ARM: dts: stm32: update slew-rate properties for sdmmc1 on stm32mp157 Yann Gautier
2019-11-06 10:09 ` [PATCH 2/4] ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC Yann Gautier
2019-11-06 10:09 ` [PATCH 3/4] ARM: dts: stm32: enable sdmmc2 node for stm32mp157c-ed1 board Yann Gautier
2019-11-06 10:09 ` [PATCH 4/4] ARM: dts: stm32: add sdmmc3 node for STM32MP1 boards Yann Gautier
2019-11-15 10:50 ` [PATCH 0/4] Update sdmmc nodes for STM32MP1 Alexandre Torgue
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).