From: Dave Gerlach <d-gerlach@ti.com>
To: Grygorii Strashko <grygorii.strashko@ti.com>,
Rob Herring <robh+dt@kernel.org>, Nishanth Menon <nm@ti.com>
Cc: <devicetree@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tony Lindgren <tony@atomide.com>, Sekhar Nori <nsekhar@ti.com>,
Kishon Vijay Abraham <kishon@ti.com>,
Lokesh Vutla <lokeshvutla@ti.com>,
Aswath Govindraju <a-govindraju@ti.com>,
Suman Anna <s-anna@ti.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/3] arm64: dts: ti: Add Support for AM642 SoC
Date: Mon, 4 Jan 2021 21:52:47 -0600 [thread overview]
Message-ID: <e3cd0241-13d3-377f-8601-92c9cdf071f1@ti.com> (raw)
In-Reply-To: <0dd0729c-ef88-4d8e-48e7-fab11afb16aa@ti.com>
Hi,
On 12/4/20 7:17 AM, Grygorii Strashko wrote:
>
>
> On 25/11/2020 07:20, Dave Gerlach wrote:
>> The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
>> providing advanced system integration to enable applications such as
>> Motor Drives, PLC, Remote IO and IoT Gateways.
>>
>> Some highlights of this SoC are:
>> * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
>> MCUs, and a single Cortex-M4F.
>> * Two Gigabit Industrial Communication Subsystems (ICSSG).
>> * Integrated Ethernet switch supporting up to a total of two external
>> ports.
>> * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
>> controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
>> peripherals.
>> * Centralized System Controller for Security, Power, and Resource
>> Management (DMSC).
>>
>> See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
>> for further details: https://www.ti.com/lit/pdf/spruim2
>>
>> Introduce basic support for the AM642 SoC to enable minimal
>> ramdisk boot. Introduce a limited set of MAIN domain periperhals
>> under cbass_main and a placeholder cbass_mcu node for future MCU
>> domain usage.
>>
>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 178 +++++++++++++++++++++++
>> arch/arm64/boot/dts/ti/k3-am64.dtsi | 95 ++++++++++++
>> arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++++++
>> 3 files changed, 338 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> new file mode 100644
>> index 000000000000..4830a8e4d89b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> @@ -0,0 +1,178 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for AM642 SoC Family Main Domain peripherals
>> + *
>> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +&cbass_main {
>> + gic500: interrupt-controller@1800000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
>> + <0x00 0x01840000 0x00 0xC0000>; /* GICR */
>> + /*
>> + * vcpumntirq:
>> + * virtual CPU interface maintenance interrupt
>> + */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + gic_its: msi-controller@1820000 {
>> + compatible = "arm,gic-v3-its";
>> + reg = <0x00 0x01820000 0x00 0x10000>;
>> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
>> + msi-controller;
>> + #msi-cells = <1>;
>> + };
>> + };
>> +
>> + dmss {
>> + compatible = "simple-mfd";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + dma-ranges;
>> + ranges;
>> +
>> + secure_proxy_main: mailbox@4d000000 {
>> + compatible = "ti,am654-secure-proxy";
>> + #mbox-cells = <1>;
>> + reg-names = "target_data", "rt", "scfg";
>> + reg = <0x00 0x4d000000 0x00 0x80000>,
>> + <0x00 0x4a600000 0x00 0x80000>,
>> + <0x00 0x4a400000 0x00 0x80000>;
>> + interrupt-names = "rx_012";
>> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>> + dmsc: dmsc {
>> + compatible = "ti,k2g-sci";
>> + ti,host-id = <12>;
>> + mbox-names = "rx", "tx";
>> + mboxes= <&secure_proxy_main 12>,
>> + <&secure_proxy_main 13>;
>> +
>> + k3_pds: power-controller {
>> + compatible = "ti,sci-pm-domain";
>> + #power-domain-cells = <2>;
>> + };
>> +
>> + k3_clks: clocks {
>> + compatible = "ti,k2g-sci-clk";
>> + #clock-cells = <2>;
>> + };
>> +
>> + k3_reset: reset-controller {
>> + compatible = "ti,sci-reset";
>> + #reset-cells = <2>;
>> + };
>> + };
>> +
>> + main_pmx0: pinctrl@f4000 {
>> + compatible = "pinctrl-single";
>> + reg = <0x00 0xf4000 0x00 0x2e4>;
>> + #pinctrl-cells = <1>;
>> + pinctrl-single,register-width = <32>;
>> + pinctrl-single,function-mask = <0xffffffff>;
>> + };
>> +
>> + chipid@43000014 {
>> + compatible = "ti,am654-chipid";
>> + reg = <0x00 0x43000014 0x00 0x4>;
>> + };
>
> Could you add proper syscon node for CTRL_MMR and place chipid under it, pls?
Sure this is no problem for v2, will do.
Regards,
Dave
next prev parent reply other threads:[~2021-01-05 3:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 5:20 [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Dave Gerlach
2020-11-25 5:20 ` [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM642 SoC Dave Gerlach
2020-12-08 16:03 ` Rob Herring
2020-11-25 5:20 ` [PATCH 2/3] arm64: dts: ti: Add Support " Dave Gerlach
2020-12-03 21:56 ` Suman Anna
2020-12-03 22:00 ` Suman Anna
2021-01-05 4:02 ` Dave Gerlach
2021-01-05 15:12 ` Nishanth Menon
2021-01-05 15:53 ` Dave Gerlach
2021-01-05 16:14 ` Nishanth Menon
2020-12-04 13:17 ` Grygorii Strashko
2021-01-05 3:52 ` Dave Gerlach [this message]
2021-01-05 7:19 ` Vignesh Raghavendra
2020-11-25 5:20 ` [PATCH 3/3] arm64: dts: ti: Add support for AM642 EVM Dave Gerlach
2020-11-27 12:40 ` [PATCH 0/3] arm64: Initial support for Texas Instruments AM642 Platform Peter Ujfalusi
2020-11-27 14:25 ` Nishanth Menon
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