From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7454C43603 for ; Tue, 10 Dec 2019 02:46:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7FC512073D for ; Tue, 10 Dec 2019 02:46:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726682AbfLJCqL (ORCPT ); Mon, 9 Dec 2019 21:46:11 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:48644 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726509AbfLJCqL (ORCPT ); Mon, 9 Dec 2019 21:46:11 -0500 Received: from [10.28.39.99] (10.28.39.99) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Tue, 10 Dec 2019 10:46:42 +0800 Subject: Re: [PATCH] arm64: dts: meson-a1: add I2C nodes To: Kevin Hilman , Jerome Brunet , Neil Armstrong CC: Rob Herring , Martin Blumenstingl , Michael Turquette , Wolfram Sang , Mark Rutland , Jianxin Pan , , , , , References: <20191202111253.94872-1-jian.hu@amlogic.com> <7hsgltqfdx.fsf@baylibre.com> From: Jian Hu Message-ID: Date: Tue, 10 Dec 2019 10:46:41 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <7hsgltqfdx.fsf@baylibre.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.28.39.99] X-ClientProxiedBy: mail-sz.amlogic.com (10.28.11.5) To mail-sz.amlogic.com (10.28.11.5) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Kevin Thanks for your review On 2019/12/10 6:54, Kevin Hilman wrote: > Hi Jian, > > Jian Hu writes: > >> There are four I2C controllers in A1 series, >> Share the same comptible with AXG.The I2C nodes >> depend on pinmux and clock controller. >> >> Signed-off-by: Jian Hu >> --- >> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ >> 1 file changed, 149 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> index eab2ecd36aa8..d0a73d953f5e 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> @@ -16,6 +16,13 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c0 = &i2c0; >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + }; >> + >> cpus { >> #address-cells = <2>; >> #size-cells = <0>; >> @@ -117,6 +124,46 @@ >> }; >> }; >> >> + i2c0: i2c@1400 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x1400 0x0 0x24>; > > The AXG DT files use 0x20 for the length. You are using 0x24. I don't > see any additional registers added to the driver, so this doesn't look right. In fact, For G12 series and A1, the length should be 0x24. A new register is added, And it is for IRQ handler timeout. If the transmission is exceeding a limited time, it will abort the transmission.Now the function is not used, There is completion to deal the timeout in the driver. I will set the length 0x20 becouse of the new register is not used. > >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_A>; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@5c00 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x5c00 0x0 0x24>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_B>; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@6800 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x6800 0x0 0x24>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_C>; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@6c00 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x6c00 0x0 0x24>; >> + interrupts = ; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_D>; >> + status = "disabled"; >> + }; >> + >> uart_AO: serial@1c00 { >> compatible = "amlogic,meson-gx-uart", >> "amlogic,meson-ao-uart"; >> @@ -171,3 +218,105 @@ >> #clock-cells = <0>; >> }; >> }; >> + >> +&periphs_pinctrl { >> + i2c0_f11_pins:i2c0-f11 { >> + mux { >> + groups = "i2c0_sck_f11", >> + "i2c0_sda_f12"; >> + function = "i2c0"; >> + bias-pull-up; >> + drive-strength-microamp = <3000>; > > Can you also add some comment to the changelog about the need for > drive-strength compared to AXG. OK, Drive strength function is added for GPIO pins from G12 series. So does A1 series. > >> + }; >> + }; > > Kevin > > . >