From: Dmitry Osipenko <digetx@gmail.com>
To: Krishna Reddy <vdumpa@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Nicolin Chen <nicolinc@nvidia.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v2 0/5] iommu: Support identity mappings of reserved-memory regions
Date: Thu, 29 Apr 2021 15:43:40 +0300 [thread overview]
Message-ID: <ea07db7b-e932-8d7d-0240-625b6e5aa765@gmail.com> (raw)
In-Reply-To: <BY5PR12MB3764DC583BC2AFE0CA674DDFB35F9@BY5PR12MB3764.namprd12.prod.outlook.com>
29.04.2021 08:51, Krishna Reddy пишет:
> Hi Dmitry,
>
>> Thank you for the answer. Could you please give more information about:
>> 1) Are you on software or hardware team, or both?
>
> I am in the software team and has contributed to initial Tegra SMMU driver in the downstream along with earlier team member Hiroshi Doyu.
>
>> 2) Is SMMU a third party IP or developed in-house?
>
> Tegra SMMU is developed in-house.
>
>> 3) Do you have a direct access to HDL sources? Are you 100% sure that
>> hardware does what you say?
>
> It was discussed with Hardware team before and again today as well.
> Enabling ASID for display engine while it continues to access the buffer memory is a safe operation.
> As per HW team, The only side-effect that can happen is additional latency to transaction as SMMU caches get warmed up.
>
>> 4) What happens when CPU writes to ASID register? Does SMMU state machine
>> latch ASID status (making it visible) only at a single "safe" point?
>
> MC makes a decision on routing transaction through either SMMU page tables or bypassing based on the ASID register value. It
> checks the ASID register only once per transaction in the pipeline.
Thank you very much for the clarification.
next prev parent reply other threads:[~2021-04-29 12:43 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-23 16:32 [PATCH v2 0/5] iommu: Support identity mappings of reserved-memory regions Thierry Reding
2021-04-23 16:32 ` [PATCH v2 1/5] dt-bindings: reserved-memory: Document memory region specifier Thierry Reding
2021-05-20 22:03 ` Rob Herring
2021-05-28 16:54 ` Thierry Reding
2021-06-08 16:51 ` Thierry Reding
2021-07-01 18:14 ` Thierry Reding
2021-07-02 14:16 ` Dmitry Osipenko
2021-09-01 14:13 ` Thierry Reding
2021-09-03 13:20 ` Rob Herring
2021-09-03 13:52 ` Thierry Reding
2021-09-03 14:36 ` Rob Herring
2021-09-03 15:35 ` Thierry Reding
2021-09-07 15:33 ` Rob Herring
2021-09-07 17:44 ` Thierry Reding
2021-09-15 15:19 ` Thierry Reding
2022-02-06 22:27 ` Janne Grunau
2022-02-09 16:31 ` Thierry Reding
2022-02-10 23:15 ` Janne Grunau
2022-03-31 16:25 ` Thierry Reding
2022-04-01 17:08 ` Janne Grunau
2021-04-23 16:32 ` [PATCH v2 2/5] iommu: Implement of_iommu_get_resv_regions() Thierry Reding
2021-07-02 14:05 ` Dmitry Osipenko
2021-07-16 14:41 ` Rob Herring
2021-07-17 11:07 ` Dmitry Osipenko
2021-07-30 12:18 ` Will Deacon
2021-04-23 16:32 ` [PATCH v2 3/5] iommu: dma: Use of_iommu_get_resv_regions() Thierry Reding
2021-04-23 16:32 ` [PATCH v2 4/5] iommu/tegra-smmu: Add support for reserved regions Thierry Reding
2021-04-23 16:32 ` [PATCH v2 5/5] iommu/tegra-smmu: Support managed domains Thierry Reding
2021-10-11 23:25 ` Dmitry Osipenko
2021-04-24 7:26 ` [PATCH v2 0/5] iommu: Support identity mappings of reserved-memory regions Dmitry Osipenko
2021-04-27 18:30 ` Krishna Reddy
2021-04-28 5:44 ` Dmitry Osipenko
2021-04-29 5:51 ` Krishna Reddy
2021-04-29 12:43 ` Dmitry Osipenko [this message]
2021-04-28 5:51 ` Dmitry Osipenko
2021-04-28 5:57 ` Mikko Perttunen
2021-04-28 7:55 ` Dmitry Osipenko
2021-04-28 5:59 ` Dmitry Osipenko
2021-10-03 1:09 ` Dmitry Osipenko
2021-10-04 19:23 ` Thierry Reding
2021-10-04 20:32 ` Dmitry Osipenko
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