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Subject: Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
To:     Anup Patel <anup@brainfault.org>, Atish Patra <atish.patra@wdc.com>
Cc:     devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
        Cyril.Jean@microchip.com,
        Daire McNamara <daire.mcnamara@microchip.com>,
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        Padmarao Begari <padmarao.begari@microchip.com>
References: <20201028232759.1928479-1-atish.patra@wdc.com>
 <20201028232759.1928479-4-atish.patra@wdc.com>
 <CAAhSdy0bgeCLYNTELdyFPj9_W1N6kDTwS6rUmLLnM=N3pTAp0g@mail.gmail.com>
From:   Ben Dooks <ben.dooks@codethink.co.uk>
Organization: Codethink Limited.
Message-ID: <f070bd74-1a5a-0559-0c37-10c9a62b82ff@codethink.co.uk>
Date:   Fri, 30 Oct 2020 21:21:37 +0000
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On 30/10/2020 09:09, Anup Patel wrote:
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>
>> Enable Microchip PolarFire ICICLE soc config in defconfig.
>> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> ---

Is there going to be a git tree with all the necessary support for the
polarfire/icicle boards? I so far have updated yocto patches, a rebase
to v5.9 and the v17 PCIe patches (which still don't work for us)

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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