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Message-ID: <f86ecad9d46fa5ca2d92e314a9e3981ae4384da1.camel@pengutronix.de>
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Marek Vasut <marex@denx.de>, Shawn Guo <shawnguo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>
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Date:   Wed, 30 Sep 2020 18:23:04 +0200
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Subject: Re: [PATCH 07/11] soc: imx: gpcv2: add support for optional resets
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On Mi, 2020-09-30 at 18:15 +0200, Marek Vasut wrote:
> On 9/30/20 5:50 PM, Lucas Stach wrote:
> > Normally the reset for the devices inside the power domain is
> > triggered automatically from the PGC in the power-up sequencing,
> > however on i.MX8MM this doesn't work for the GPU power domains.
> 
> One has to wonder whether the VPU power domain has similar hardware bug
> on the MX8MM ?

Nope the VPUs have separate reset bits in the BLK_CTL. So after
powering up the VPUMIX domain one can assert/deassert reset to the
individual VPU cores.

Regards,
Lucas

> [...]
> 
> > @@ -112,6 +113,7 @@ struct imx_pgc_domain {
> >  	struct regulator *regulator;
> >  	struct clk *clk[GPC_CLK_MAX];
> >  	int num_clks;
> > +	struct reset_control *reset;
> 
> Keep this sorted as reverse xmas tree please.

Triggering some OCD, here? ;) Will do.

Regards,
Lucas