From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F300CC43603 for ; Thu, 19 Dec 2019 13:13:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF7A620716 for ; Thu, 19 Dec 2019 13:13:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GK1cbM7H" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726760AbfLSNNR (ORCPT ); Thu, 19 Dec 2019 08:13:17 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:56236 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726695AbfLSNNR (ORCPT ); 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Thu, 19 Dec 2019 07:13:06 -0600 Received: from [10.24.69.159] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBJDD38D090087; Thu, 19 Dec 2019 07:13:03 -0600 Subject: Re: [PATCH 10/13] dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC To: Rob Herring , Tom Joseph CC: Bjorn Helgaas , Lorenzo Pieralisi , Arnd Bergmann , Andrew Murray , , , , References: <20191209092147.22901-1-kishon@ti.com> <20191209092147.22901-11-kishon@ti.com> <20191219001408.GA20303@bogus> From: Kishon Vijay Abraham I Message-ID: Date: Thu, 19 Dec 2019 18:44:46 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20191219001408.GA20303@bogus> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org +Tom On 19/12/19 5:44 am, Rob Herring wrote: > On Mon, Dec 09, 2019 at 02:51:44PM +0530, Kishon Vijay Abraham I wrote: >> Add PCIe EP mode dt-bindings for TI's J721E SoC. >> >> Cc: Rob Herring >> Signed-off-by: Kishon Vijay Abraham I >> --- >> .../bindings/pci/ti,j721e-pci-ep.yaml | 113 ++++++++++++++++++ >> 1 file changed, 113 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> >> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> new file mode 100644 >> index 000000000000..4e2af4733998 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml >> @@ -0,0 +1,113 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: TI J721E PCI EP (PCIe Wrapper) >> + >> +maintainers: >> + - Kishon Vijay Abraham I >> + >> +properties: >> + compatible: >> + enum: >> + - ti,j721e-pcie-ep > > Indentation. > >> + >> + reg: >> + maxItems: 4 >> + >> + reg-names: >> + items: >> + - const: intd_cfg >> + - const: user_cfg >> + - const: reg >> + - const: mem >> + >> + ti,syscon-pcie-ctrl: >> + description: Phandle to the SYSCON entry required for configuring PCIe mode >> + and link speed. >> + allOf: >> + - $ref: /schemas/types.yaml#/definitions/phandle >> + >> + max-link-speed: >> + minimum: 1 >> + maximum: 3 >> + >> + num-lanes: >> + minimum: 1 >> + maximum: 2 >> + >> + power-domains: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + description: clock-specifier to represent input to the PCIe >> + >> + clock-names: >> + items: >> + - const: fck >> + >> + cdns,max-outbound-regions: >> + description: As defined in >> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >> + allOf: >> + - $ref: /schemas/types.yaml#/definitions/int32 > > uint32 > >> + - enum: [16] >> + >> + max-functions: >> + minimum: 1 >> + maximum: 6 > > Needs a type ref. Or a common definition. > >> + >> + dma-coherent: >> + description: Indicates that the PCIe IP block can ensure the coherency >> + >> + phys: > > How many? Need to convert cdns,cdns-pcie-host.txt... Tom, Can you convert cdns,cdns-pcie-host.txt to YAML binding? > >> + description: As defined in >> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt >> + >> + phy-names: >> + description: As defined in >> + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt > > For all the properties shared with host mode, it might make sense to > define a common schema with all those properties and then include it in > the host and endpoint schemas. Sure. Thanks Kishon